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1 // Copyright 2013 the V8 project authors. All rights reserved. | 1 // Copyright 2013 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #ifndef V8_ARM64_MACRO_ASSEMBLER_ARM64_H_ | 5 #ifndef V8_ARM64_MACRO_ASSEMBLER_ARM64_H_ |
6 #define V8_ARM64_MACRO_ASSEMBLER_ARM64_H_ | 6 #define V8_ARM64_MACRO_ASSEMBLER_ARM64_H_ |
7 | 7 |
8 #include <vector> | 8 #include <vector> |
9 | 9 |
10 #include "src/arm64/assembler-arm64.h" | 10 #include "src/arm64/assembler-arm64.h" |
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389 const Register& rn, | 389 const Register& rn, |
390 const Register& rm, | 390 const Register& rm, |
391 Condition cond); | 391 Condition cond); |
392 inline void Dmb(BarrierDomain domain, BarrierType type); | 392 inline void Dmb(BarrierDomain domain, BarrierType type); |
393 inline void Dsb(BarrierDomain domain, BarrierType type); | 393 inline void Dsb(BarrierDomain domain, BarrierType type); |
394 inline void Debug(const char* message, uint32_t code, Instr params = BREAK); | 394 inline void Debug(const char* message, uint32_t code, Instr params = BREAK); |
395 inline void Extr(const Register& rd, | 395 inline void Extr(const Register& rd, |
396 const Register& rn, | 396 const Register& rn, |
397 const Register& rm, | 397 const Register& rm, |
398 unsigned lsb); | 398 unsigned lsb); |
399 inline void Fabs(const FPRegister& fd, const FPRegister& fn); | 399 inline void Fabs(const VRegister& fd, const VRegister& fn); |
400 inline void Fadd(const FPRegister& fd, | 400 inline void Fadd(const VRegister& fd, const VRegister& fn, |
401 const FPRegister& fn, | 401 const VRegister& fm); |
402 const FPRegister& fm); | 402 inline void Fccmp(const VRegister& fn, const VRegister& fm, StatusFlags nzcv, |
403 inline void Fccmp(const FPRegister& fn, | |
404 const FPRegister& fm, | |
405 StatusFlags nzcv, | |
406 Condition cond); | 403 Condition cond); |
407 inline void Fcmp(const FPRegister& fn, const FPRegister& fm); | 404 inline void Fcmp(const VRegister& fn, const VRegister& fm); |
408 inline void Fcmp(const FPRegister& fn, double value); | 405 inline void Fcmp(const VRegister& fn, double value); |
409 inline void Fcsel(const FPRegister& fd, | 406 inline void Fcsel(const VRegister& fd, const VRegister& fn, |
410 const FPRegister& fn, | 407 const VRegister& fm, Condition cond); |
411 const FPRegister& fm, | 408 inline void Fcvt(const VRegister& fd, const VRegister& fn); |
412 Condition cond); | 409 void Fcvtl(const VRegister& vd, const VRegister& vn) { |
413 inline void Fcvt(const FPRegister& fd, const FPRegister& fn); | 410 DCHECK(allow_macro_instructions_); |
414 inline void Fcvtas(const Register& rd, const FPRegister& fn); | 411 fcvtl(vd, vn); |
415 inline void Fcvtau(const Register& rd, const FPRegister& fn); | 412 } |
416 inline void Fcvtms(const Register& rd, const FPRegister& fn); | 413 void Fcvtl2(const VRegister& vd, const VRegister& vn) { |
417 inline void Fcvtmu(const Register& rd, const FPRegister& fn); | 414 DCHECK(allow_macro_instructions_); |
418 inline void Fcvtns(const Register& rd, const FPRegister& fn); | 415 fcvtl2(vd, vn); |
419 inline void Fcvtnu(const Register& rd, const FPRegister& fn); | 416 } |
420 inline void Fcvtzs(const Register& rd, const FPRegister& fn); | 417 void Fcvtn(const VRegister& vd, const VRegister& vn) { |
421 inline void Fcvtzu(const Register& rd, const FPRegister& fn); | 418 DCHECK(allow_macro_instructions_); |
422 inline void Fdiv(const FPRegister& fd, | 419 fcvtn(vd, vn); |
423 const FPRegister& fn, | 420 } |
424 const FPRegister& fm); | 421 void Fcvtn2(const VRegister& vd, const VRegister& vn) { |
425 inline void Fmadd(const FPRegister& fd, | 422 DCHECK(allow_macro_instructions_); |
426 const FPRegister& fn, | 423 fcvtn2(vd, vn); |
427 const FPRegister& fm, | 424 } |
428 const FPRegister& fa); | 425 void Fcvtxn(const VRegister& vd, const VRegister& vn) { |
429 inline void Fmax(const FPRegister& fd, | 426 DCHECK(allow_macro_instructions_); |
430 const FPRegister& fn, | 427 fcvtxn(vd, vn); |
431 const FPRegister& fm); | 428 } |
432 inline void Fmaxnm(const FPRegister& fd, | 429 void Fcvtxn2(const VRegister& vd, const VRegister& vn) { |
433 const FPRegister& fn, | 430 DCHECK(allow_macro_instructions_); |
434 const FPRegister& fm); | 431 fcvtxn2(vd, vn); |
435 inline void Fmin(const FPRegister& fd, | 432 } |
436 const FPRegister& fn, | 433 inline void Fcvtas(const Register& rd, const VRegister& fn); |
437 const FPRegister& fm); | 434 inline void Fcvtau(const Register& rd, const VRegister& fn); |
438 inline void Fminnm(const FPRegister& fd, | 435 inline void Fcvtms(const Register& rd, const VRegister& fn); |
439 const FPRegister& fn, | 436 inline void Fcvtmu(const Register& rd, const VRegister& fn); |
440 const FPRegister& fm); | 437 inline void Fcvtns(const Register& rd, const VRegister& fn); |
441 inline void Fmov(FPRegister fd, FPRegister fn); | 438 inline void Fcvtnu(const Register& rd, const VRegister& fn); |
442 inline void Fmov(FPRegister fd, Register rn); | 439 inline void Fcvtzs(const Register& rd, const VRegister& fn); |
| 440 inline void Fcvtzu(const Register& rd, const VRegister& fn); |
| 441 inline void Fdiv(const VRegister& fd, const VRegister& fn, |
| 442 const VRegister& fm); |
| 443 inline void Fmadd(const VRegister& fd, const VRegister& fn, |
| 444 const VRegister& fm, const VRegister& fa); |
| 445 inline void Fmax(const VRegister& fd, const VRegister& fn, |
| 446 const VRegister& fm); |
| 447 inline void Fmaxnm(const VRegister& fd, const VRegister& fn, |
| 448 const VRegister& fm); |
| 449 inline void Fmin(const VRegister& fd, const VRegister& fn, |
| 450 const VRegister& fm); |
| 451 inline void Fminnm(const VRegister& fd, const VRegister& fn, |
| 452 const VRegister& fm); |
| 453 inline void Fmov(VRegister fd, VRegister fn); |
| 454 inline void Fmov(VRegister fd, Register rn); |
443 // Provide explicit double and float interfaces for FP immediate moves, rather | 455 // Provide explicit double and float interfaces for FP immediate moves, rather |
444 // than relying on implicit C++ casts. This allows signalling NaNs to be | 456 // than relying on implicit C++ casts. This allows signalling NaNs to be |
445 // preserved when the immediate matches the format of fd. Most systems convert | 457 // preserved when the immediate matches the format of fd. Most systems convert |
446 // signalling NaNs to quiet NaNs when converting between float and double. | 458 // signalling NaNs to quiet NaNs when converting between float and double. |
447 inline void Fmov(FPRegister fd, double imm); | 459 inline void Fmov(VRegister fd, double imm); |
448 inline void Fmov(FPRegister fd, float imm); | 460 inline void Fmov(VRegister fd, float imm); |
449 // Provide a template to allow other types to be converted automatically. | 461 // Provide a template to allow other types to be converted automatically. |
450 template<typename T> | 462 template <typename T> |
451 void Fmov(FPRegister fd, T imm) { | 463 void Fmov(VRegister fd, T imm) { |
452 DCHECK(allow_macro_instructions_); | 464 DCHECK(allow_macro_instructions_); |
453 Fmov(fd, static_cast<double>(imm)); | 465 Fmov(fd, static_cast<double>(imm)); |
454 } | 466 } |
455 inline void Fmov(Register rd, FPRegister fn); | 467 inline void Fmov(Register rd, VRegister fn); |
456 inline void Fmsub(const FPRegister& fd, | 468 inline void Fmsub(const VRegister& fd, const VRegister& fn, |
457 const FPRegister& fn, | 469 const VRegister& fm, const VRegister& fa); |
458 const FPRegister& fm, | 470 inline void Fmul(const VRegister& fd, const VRegister& fn, |
459 const FPRegister& fa); | 471 const VRegister& fm); |
460 inline void Fmul(const FPRegister& fd, | 472 inline void Fnmadd(const VRegister& fd, const VRegister& fn, |
461 const FPRegister& fn, | 473 const VRegister& fm, const VRegister& fa); |
462 const FPRegister& fm); | 474 inline void Fnmsub(const VRegister& fd, const VRegister& fn, |
463 inline void Fneg(const FPRegister& fd, const FPRegister& fn); | 475 const VRegister& fm, const VRegister& fa); |
464 inline void Fnmadd(const FPRegister& fd, | 476 inline void Fsub(const VRegister& fd, const VRegister& fn, |
465 const FPRegister& fn, | 477 const VRegister& fm); |
466 const FPRegister& fm, | |
467 const FPRegister& fa); | |
468 inline void Fnmsub(const FPRegister& fd, | |
469 const FPRegister& fn, | |
470 const FPRegister& fm, | |
471 const FPRegister& fa); | |
472 inline void Frinta(const FPRegister& fd, const FPRegister& fn); | |
473 inline void Frintm(const FPRegister& fd, const FPRegister& fn); | |
474 inline void Frintn(const FPRegister& fd, const FPRegister& fn); | |
475 inline void Frintp(const FPRegister& fd, const FPRegister& fn); | |
476 inline void Frintz(const FPRegister& fd, const FPRegister& fn); | |
477 inline void Fsqrt(const FPRegister& fd, const FPRegister& fn); | |
478 inline void Fsub(const FPRegister& fd, | |
479 const FPRegister& fn, | |
480 const FPRegister& fm); | |
481 inline void Hint(SystemHint code); | 478 inline void Hint(SystemHint code); |
482 inline void Hlt(int code); | 479 inline void Hlt(int code); |
483 inline void Isb(); | 480 inline void Isb(); |
484 inline void Ldnp(const CPURegister& rt, | 481 inline void Ldnp(const CPURegister& rt, |
485 const CPURegister& rt2, | 482 const CPURegister& rt2, |
486 const MemOperand& src); | 483 const MemOperand& src); |
487 // Load a literal from the inline constant pool. | 484 // Load a literal from the inline constant pool. |
488 inline void Ldr(const CPURegister& rt, const Immediate& imm); | 485 inline void Ldr(const CPURegister& rt, const Immediate& imm); |
489 // Helper function for double immediate. | 486 // Helper function for double immediate. |
490 inline void Ldr(const CPURegister& rt, double imm); | 487 inline void Ldr(const CPURegister& rt, double imm); |
491 inline void Lsl(const Register& rd, const Register& rn, unsigned shift); | 488 inline void Lsl(const Register& rd, const Register& rn, unsigned shift); |
492 inline void Lsl(const Register& rd, const Register& rn, const Register& rm); | 489 inline void Lsl(const Register& rd, const Register& rn, const Register& rm); |
493 inline void Lsr(const Register& rd, const Register& rn, unsigned shift); | 490 inline void Lsr(const Register& rd, const Register& rn, unsigned shift); |
494 inline void Lsr(const Register& rd, const Register& rn, const Register& rm); | 491 inline void Lsr(const Register& rd, const Register& rn, const Register& rm); |
495 inline void Madd(const Register& rd, | 492 inline void Madd(const Register& rd, |
496 const Register& rn, | 493 const Register& rn, |
497 const Register& rm, | 494 const Register& rm, |
498 const Register& ra); | 495 const Register& ra); |
499 inline void Mneg(const Register& rd, const Register& rn, const Register& rm); | 496 inline void Mneg(const Register& rd, const Register& rn, const Register& rm); |
500 inline void Mov(const Register& rd, const Register& rm); | 497 inline void Mov(const Register& rd, const Register& rm); |
501 inline void Movk(const Register& rd, uint64_t imm, int shift = -1); | 498 inline void Movk(const Register& rd, uint64_t imm, int shift = -1); |
502 inline void Mrs(const Register& rt, SystemRegister sysreg); | 499 inline void Mrs(const Register& rt, SystemRegister sysreg); |
503 inline void Msr(SystemRegister sysreg, const Register& rt); | 500 inline void Msr(SystemRegister sysreg, const Register& rt); |
504 inline void Msub(const Register& rd, | 501 inline void Msub(const Register& rd, |
505 const Register& rn, | 502 const Register& rn, |
506 const Register& rm, | 503 const Register& rm, |
507 const Register& ra); | 504 const Register& ra); |
508 inline void Mul(const Register& rd, const Register& rn, const Register& rm); | 505 inline void Mul(const Register& rd, const Register& rn, const Register& rm); |
509 inline void Nop() { nop(); } | 506 inline void Nop() { nop(); } |
| 507 void Dup(const VRegister& vd, const VRegister& vn, int index) { |
| 508 DCHECK(allow_macro_instructions_); |
| 509 dup(vd, vn, index); |
| 510 } |
| 511 void Dup(const VRegister& vd, const Register& rn) { |
| 512 DCHECK(allow_macro_instructions_); |
| 513 dup(vd, rn); |
| 514 } |
| 515 void Ins(const VRegister& vd, int vd_index, const VRegister& vn, |
| 516 int vn_index) { |
| 517 DCHECK(allow_macro_instructions_); |
| 518 ins(vd, vd_index, vn, vn_index); |
| 519 } |
| 520 void Ins(const VRegister& vd, int vd_index, const Register& rn) { |
| 521 DCHECK(allow_macro_instructions_); |
| 522 ins(vd, vd_index, rn); |
| 523 } |
| 524 void Mov(const VRegister& vd, int vd_index, const VRegister& vn, |
| 525 int vn_index) { |
| 526 DCHECK(allow_macro_instructions_); |
| 527 mov(vd, vd_index, vn, vn_index); |
| 528 } |
| 529 void Mov(const VRegister& vd, const VRegister& vn, int index) { |
| 530 DCHECK(allow_macro_instructions_); |
| 531 mov(vd, vn, index); |
| 532 } |
| 533 void Mov(const VRegister& vd, int vd_index, const Register& rn) { |
| 534 DCHECK(allow_macro_instructions_); |
| 535 mov(vd, vd_index, rn); |
| 536 } |
| 537 void Mov(const Register& rd, const VRegister& vn, int vn_index) { |
| 538 DCHECK(allow_macro_instructions_); |
| 539 mov(rd, vn, vn_index); |
| 540 } |
| 541 void Movi(const VRegister& vd, uint64_t imm, Shift shift = LSL, |
| 542 int shift_amount = 0); |
| 543 void Movi(const VRegister& vd, uint64_t hi, uint64_t lo); |
| 544 void Mvni(const VRegister& vd, const int imm8, Shift shift = LSL, |
| 545 const int shift_amount = 0) { |
| 546 DCHECK(allow_macro_instructions_); |
| 547 mvni(vd, imm8, shift, shift_amount); |
| 548 } |
| 549 void Orr(const VRegister& vd, const int imm8, const int left_shift = 0) { |
| 550 DCHECK(allow_macro_instructions_); |
| 551 orr(vd, imm8, left_shift); |
| 552 } |
| 553 void Scvtf(const VRegister& vd, const VRegister& vn, int fbits = 0) { |
| 554 DCHECK(allow_macro_instructions_); |
| 555 scvtf(vd, vn, fbits); |
| 556 } |
| 557 void Ucvtf(const VRegister& vd, const VRegister& vn, int fbits = 0) { |
| 558 DCHECK(allow_macro_instructions_); |
| 559 ucvtf(vd, vn, fbits); |
| 560 } |
| 561 void Fcvtzs(const VRegister& vd, const VRegister& vn, int fbits = 0) { |
| 562 DCHECK(allow_macro_instructions_); |
| 563 fcvtzs(vd, vn, fbits); |
| 564 } |
| 565 void Fcvtzu(const VRegister& vd, const VRegister& vn, int fbits = 0) { |
| 566 DCHECK(allow_macro_instructions_); |
| 567 fcvtzu(vd, vn, fbits); |
| 568 } |
| 569 void Smov(const Register& rd, const VRegister& vn, int vn_index) { |
| 570 DCHECK(allow_macro_instructions_); |
| 571 smov(rd, vn, vn_index); |
| 572 } |
| 573 void Umov(const Register& rd, const VRegister& vn, int vn_index) { |
| 574 DCHECK(allow_macro_instructions_); |
| 575 umov(rd, vn, vn_index); |
| 576 } |
510 inline void Rbit(const Register& rd, const Register& rn); | 577 inline void Rbit(const Register& rd, const Register& rn); |
511 inline void Ret(const Register& xn = lr); | 578 inline void Ret(const Register& xn = lr); |
512 inline void Rev(const Register& rd, const Register& rn); | 579 inline void Rev(const Register& rd, const Register& rn); |
513 inline void Rev16(const Register& rd, const Register& rn); | 580 inline void Rev16(const Register& rd, const Register& rn); |
514 inline void Rev32(const Register& rd, const Register& rn); | 581 inline void Rev32(const Register& rd, const Register& rn); |
515 inline void Ror(const Register& rd, const Register& rs, unsigned shift); | 582 inline void Ror(const Register& rd, const Register& rs, unsigned shift); |
516 inline void Ror(const Register& rd, const Register& rn, const Register& rm); | 583 inline void Ror(const Register& rd, const Register& rn, const Register& rm); |
517 inline void Sbfiz(const Register& rd, | 584 inline void Sbfiz(const Register& rd, |
518 const Register& rn, | 585 const Register& rn, |
519 unsigned lsb, | 586 unsigned lsb, |
520 unsigned width); | 587 unsigned width); |
521 inline void Sbfx(const Register& rd, | 588 inline void Sbfx(const Register& rd, |
522 const Register& rn, | 589 const Register& rn, |
523 unsigned lsb, | 590 unsigned lsb, |
524 unsigned width); | 591 unsigned width); |
525 inline void Scvtf(const FPRegister& fd, | 592 inline void Scvtf(const VRegister& fd, const Register& rn, |
526 const Register& rn, | |
527 unsigned fbits = 0); | 593 unsigned fbits = 0); |
528 inline void Sdiv(const Register& rd, const Register& rn, const Register& rm); | 594 inline void Sdiv(const Register& rd, const Register& rn, const Register& rm); |
529 inline void Smaddl(const Register& rd, | 595 inline void Smaddl(const Register& rd, |
530 const Register& rn, | 596 const Register& rn, |
531 const Register& rm, | 597 const Register& rm, |
532 const Register& ra); | 598 const Register& ra); |
533 inline void Smsubl(const Register& rd, | 599 inline void Smsubl(const Register& rd, |
534 const Register& rn, | 600 const Register& rn, |
535 const Register& rm, | 601 const Register& rm, |
536 const Register& ra); | 602 const Register& ra); |
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550 void Tbnz(const Register& rt, unsigned bit_pos, Label* label); | 616 void Tbnz(const Register& rt, unsigned bit_pos, Label* label); |
551 void Tbz(const Register& rt, unsigned bit_pos, Label* label); | 617 void Tbz(const Register& rt, unsigned bit_pos, Label* label); |
552 inline void Ubfiz(const Register& rd, | 618 inline void Ubfiz(const Register& rd, |
553 const Register& rn, | 619 const Register& rn, |
554 unsigned lsb, | 620 unsigned lsb, |
555 unsigned width); | 621 unsigned width); |
556 inline void Ubfx(const Register& rd, | 622 inline void Ubfx(const Register& rd, |
557 const Register& rn, | 623 const Register& rn, |
558 unsigned lsb, | 624 unsigned lsb, |
559 unsigned width); | 625 unsigned width); |
560 inline void Ucvtf(const FPRegister& fd, | 626 inline void Ucvtf(const VRegister& fd, const Register& rn, |
561 const Register& rn, | |
562 unsigned fbits = 0); | 627 unsigned fbits = 0); |
563 inline void Udiv(const Register& rd, const Register& rn, const Register& rm); | 628 inline void Udiv(const Register& rd, const Register& rn, const Register& rm); |
564 inline void Umaddl(const Register& rd, | 629 inline void Umaddl(const Register& rd, |
565 const Register& rn, | 630 const Register& rn, |
566 const Register& rm, | 631 const Register& rm, |
567 const Register& ra); | 632 const Register& ra); |
568 inline void Umsubl(const Register& rd, | 633 inline void Umsubl(const Register& rd, |
569 const Register& rn, | 634 const Register& rn, |
570 const Register& rm, | 635 const Register& rm, |
571 const Register& ra); | 636 const Register& ra); |
572 inline void Uxtb(const Register& rd, const Register& rn); | 637 inline void Uxtb(const Register& rd, const Register& rn); |
573 inline void Uxth(const Register& rd, const Register& rn); | 638 inline void Uxth(const Register& rd, const Register& rn); |
574 inline void Uxtw(const Register& rd, const Register& rn); | 639 inline void Uxtw(const Register& rd, const Register& rn); |
575 | 640 |
| 641 // NEON 3 vector register instructions. |
| 642 #define NEON_3VREG_MACRO_LIST(V) \ |
| 643 V(add, Add) \ |
| 644 V(addhn, Addhn) \ |
| 645 V(addhn2, Addhn2) \ |
| 646 V(addp, Addp) \ |
| 647 V(and_, And) \ |
| 648 V(bic, Bic) \ |
| 649 V(bif, Bif) \ |
| 650 V(bit, Bit) \ |
| 651 V(bsl, Bsl) \ |
| 652 V(cmeq, Cmeq) \ |
| 653 V(cmge, Cmge) \ |
| 654 V(cmgt, Cmgt) \ |
| 655 V(cmhi, Cmhi) \ |
| 656 V(cmhs, Cmhs) \ |
| 657 V(cmtst, Cmtst) \ |
| 658 V(eor, Eor) \ |
| 659 V(fabd, Fabd) \ |
| 660 V(facge, Facge) \ |
| 661 V(facgt, Facgt) \ |
| 662 V(faddp, Faddp) \ |
| 663 V(fcmeq, Fcmeq) \ |
| 664 V(fcmge, Fcmge) \ |
| 665 V(fcmgt, Fcmgt) \ |
| 666 V(fmaxnmp, Fmaxnmp) \ |
| 667 V(fmaxp, Fmaxp) \ |
| 668 V(fminnmp, Fminnmp) \ |
| 669 V(fminp, Fminp) \ |
| 670 V(fmla, Fmla) \ |
| 671 V(fmls, Fmls) \ |
| 672 V(fmulx, Fmulx) \ |
| 673 V(frecps, Frecps) \ |
| 674 V(frsqrts, Frsqrts) \ |
| 675 V(mla, Mla) \ |
| 676 V(mls, Mls) \ |
| 677 V(mul, Mul) \ |
| 678 V(orn, Orn) \ |
| 679 V(pmul, Pmul) \ |
| 680 V(pmull, Pmull) \ |
| 681 V(pmull2, Pmull2) \ |
| 682 V(raddhn, Raddhn) \ |
| 683 V(raddhn2, Raddhn2) \ |
| 684 V(rsubhn, Rsubhn) \ |
| 685 V(rsubhn2, Rsubhn2) \ |
| 686 V(sqadd, Sqadd) \ |
| 687 V(sqdmlal, Sqdmlal) \ |
| 688 V(sqdmlal2, Sqdmlal2) \ |
| 689 V(sqdmulh, Sqdmulh) \ |
| 690 V(sqdmull, Sqdmull) \ |
| 691 V(sqdmull2, Sqdmull2) \ |
| 692 V(sqrdmulh, Sqrdmulh) \ |
| 693 V(sqrshl, Sqrshl) \ |
| 694 V(sqshl, Sqshl) \ |
| 695 V(sqsub, Sqsub) \ |
| 696 V(srhadd, Srhadd) \ |
| 697 V(srshl, Srshl) \ |
| 698 V(sshl, Sshl) \ |
| 699 V(ssubl, Ssubl) \ |
| 700 V(ssubl2, Ssubl2) \ |
| 701 V(ssubw, Ssubw) \ |
| 702 V(ssubw2, Ssubw2) \ |
| 703 V(sub, Sub) \ |
| 704 V(subhn, Subhn) \ |
| 705 V(subhn2, Subhn2) \ |
| 706 V(trn1, Trn1) \ |
| 707 V(trn2, Trn2) \ |
| 708 V(orr, Orr) \ |
| 709 V(saba, Saba) \ |
| 710 V(sabal, Sabal) \ |
| 711 V(sabal2, Sabal2) \ |
| 712 V(sabd, Sabd) \ |
| 713 V(sabdl, Sabdl) \ |
| 714 V(sabdl2, Sabdl2) \ |
| 715 V(saddl, Saddl) \ |
| 716 V(saddl2, Saddl2) \ |
| 717 V(saddw, Saddw) \ |
| 718 V(saddw2, Saddw2) \ |
| 719 V(shadd, Shadd) \ |
| 720 V(shsub, Shsub) \ |
| 721 V(smax, Smax) \ |
| 722 V(smaxp, Smaxp) \ |
| 723 V(smin, Smin) \ |
| 724 V(sminp, Sminp) \ |
| 725 V(smlal, Smlal) \ |
| 726 V(smlal2, Smlal2) \ |
| 727 V(smlsl, Smlsl) \ |
| 728 V(smlsl2, Smlsl2) \ |
| 729 V(smull, Smull) \ |
| 730 V(smull2, Smull2) \ |
| 731 V(sqdmlsl, Sqdmlsl) \ |
| 732 V(sqdmlsl2, Sqdmlsl2) \ |
| 733 V(uaba, Uaba) \ |
| 734 V(uabal, Uabal) \ |
| 735 V(uabal2, Uabal2) \ |
| 736 V(uabd, Uabd) \ |
| 737 V(uabdl, Uabdl) \ |
| 738 V(uabdl2, Uabdl2) \ |
| 739 V(uaddl, Uaddl) \ |
| 740 V(uaddl2, Uaddl2) \ |
| 741 V(uaddw, Uaddw) \ |
| 742 V(uaddw2, Uaddw2) \ |
| 743 V(uhadd, Uhadd) \ |
| 744 V(uhsub, Uhsub) \ |
| 745 V(umax, Umax) \ |
| 746 V(umin, Umin) \ |
| 747 V(umlsl, Umlsl) \ |
| 748 V(umlsl2, Umlsl2) \ |
| 749 V(umull, Umull) \ |
| 750 V(umull2, Umull2) \ |
| 751 V(umaxp, Umaxp) \ |
| 752 V(uminp, Uminp) \ |
| 753 V(umlal, Umlal) \ |
| 754 V(umlal2, Umlal2) \ |
| 755 V(uqadd, Uqadd) \ |
| 756 V(uqrshl, Uqrshl) \ |
| 757 V(uqshl, Uqshl) \ |
| 758 V(uqsub, Uqsub) \ |
| 759 V(urhadd, Urhadd) \ |
| 760 V(urshl, Urshl) \ |
| 761 V(ushl, Ushl) \ |
| 762 V(usubl, Usubl) \ |
| 763 V(usubl2, Usubl2) \ |
| 764 V(usubw, Usubw) \ |
| 765 V(usubw2, Usubw2) \ |
| 766 V(uzp1, Uzp1) \ |
| 767 V(uzp2, Uzp2) \ |
| 768 V(zip1, Zip1) \ |
| 769 V(zip2, Zip2) |
| 770 |
| 771 #define DEFINE_MACRO_ASM_FUNC(ASM, MASM) \ |
| 772 void MASM(const VRegister& vd, const VRegister& vn, const VRegister& vm) { \ |
| 773 DCHECK(allow_macro_instructions_); \ |
| 774 ASM(vd, vn, vm); \ |
| 775 } |
| 776 NEON_3VREG_MACRO_LIST(DEFINE_MACRO_ASM_FUNC) |
| 777 #undef DEFINE_MACRO_ASM_FUNC |
| 778 |
| 779 void Ext(const VRegister& vd, const VRegister& vn, const VRegister& vm, |
| 780 int index) { |
| 781 DCHECK(allow_macro_instructions_); |
| 782 ext(vd, vn, vm, index); |
| 783 } |
| 784 |
| 785 // NEON 2 vector register instructions. |
| 786 #define NEON_2VREG_MACRO_LIST(V) \ |
| 787 V(abs, Abs) \ |
| 788 V(addp, Addp) \ |
| 789 V(addv, Addv) \ |
| 790 V(cls, Cls) \ |
| 791 V(clz, Clz) \ |
| 792 V(cnt, Cnt) \ |
| 793 V(faddp, Faddp) \ |
| 794 V(fcvtas, Fcvtas) \ |
| 795 V(fcvtau, Fcvtau) \ |
| 796 V(fcvtms, Fcvtms) \ |
| 797 V(fcvtmu, Fcvtmu) \ |
| 798 V(fcvtns, Fcvtns) \ |
| 799 V(fcvtnu, Fcvtnu) \ |
| 800 V(fcvtps, Fcvtps) \ |
| 801 V(fcvtpu, Fcvtpu) \ |
| 802 V(fmaxnmp, Fmaxnmp) \ |
| 803 V(fmaxnmv, Fmaxnmv) \ |
| 804 V(fmaxv, Fmaxv) \ |
| 805 V(fminnmp, Fminnmp) \ |
| 806 V(fminnmv, Fminnmv) \ |
| 807 V(fminp, Fminp) \ |
| 808 V(fmaxp, Fmaxp) \ |
| 809 V(fminv, Fminv) \ |
| 810 V(fneg, Fneg) \ |
| 811 V(frecpe, Frecpe) \ |
| 812 V(frecpx, Frecpx) \ |
| 813 V(frinta, Frinta) \ |
| 814 V(frinti, Frinti) \ |
| 815 V(frintm, Frintm) \ |
| 816 V(frintn, Frintn) \ |
| 817 V(frintp, Frintp) \ |
| 818 V(frintx, Frintx) \ |
| 819 V(frintz, Frintz) \ |
| 820 V(frsqrte, Frsqrte) \ |
| 821 V(fsqrt, Fsqrt) \ |
| 822 V(mov, Mov) \ |
| 823 V(mvn, Mvn) \ |
| 824 V(neg, Neg) \ |
| 825 V(not_, Not) \ |
| 826 V(rbit, Rbit) \ |
| 827 V(rev16, Rev16) \ |
| 828 V(rev32, Rev32) \ |
| 829 V(rev64, Rev64) \ |
| 830 V(sadalp, Sadalp) \ |
| 831 V(saddlv, Saddlv) \ |
| 832 V(smaxv, Smaxv) \ |
| 833 V(sminv, Sminv) \ |
| 834 V(saddlp, Saddlp) \ |
| 835 V(sqabs, Sqabs) \ |
| 836 V(sqneg, Sqneg) \ |
| 837 V(sqxtn, Sqxtn) \ |
| 838 V(sqxtn2, Sqxtn2) \ |
| 839 V(sqxtun, Sqxtun) \ |
| 840 V(sqxtun2, Sqxtun2) \ |
| 841 V(suqadd, Suqadd) \ |
| 842 V(sxtl, Sxtl) \ |
| 843 V(sxtl2, Sxtl2) \ |
| 844 V(uadalp, Uadalp) \ |
| 845 V(uaddlp, Uaddlp) \ |
| 846 V(uaddlv, Uaddlv) \ |
| 847 V(umaxv, Umaxv) \ |
| 848 V(uminv, Uminv) \ |
| 849 V(uqxtn, Uqxtn) \ |
| 850 V(uqxtn2, Uqxtn2) \ |
| 851 V(urecpe, Urecpe) \ |
| 852 V(ursqrte, Ursqrte) \ |
| 853 V(usqadd, Usqadd) \ |
| 854 V(uxtl, Uxtl) \ |
| 855 V(uxtl2, Uxtl2) \ |
| 856 V(xtn, Xtn) \ |
| 857 V(xtn2, Xtn2) |
| 858 |
| 859 #define DEFINE_MACRO_ASM_FUNC(ASM, MASM) \ |
| 860 void MASM(const VRegister& vd, const VRegister& vn) { \ |
| 861 DCHECK(allow_macro_instructions_); \ |
| 862 ASM(vd, vn); \ |
| 863 } |
| 864 NEON_2VREG_MACRO_LIST(DEFINE_MACRO_ASM_FUNC) |
| 865 #undef DEFINE_MACRO_ASM_FUNC |
| 866 |
| 867 // NEON 2 vector register with immediate instructions. |
| 868 #define NEON_2VREG_FPIMM_MACRO_LIST(V) \ |
| 869 V(fcmeq, Fcmeq) \ |
| 870 V(fcmge, Fcmge) \ |
| 871 V(fcmgt, Fcmgt) \ |
| 872 V(fcmle, Fcmle) \ |
| 873 V(fcmlt, Fcmlt) |
| 874 |
| 875 #define DEFINE_MACRO_ASM_FUNC(ASM, MASM) \ |
| 876 void MASM(const VRegister& vd, const VRegister& vn, double imm) { \ |
| 877 DCHECK(allow_macro_instructions_); \ |
| 878 ASM(vd, vn, imm); \ |
| 879 } |
| 880 NEON_2VREG_FPIMM_MACRO_LIST(DEFINE_MACRO_ASM_FUNC) |
| 881 #undef DEFINE_MACRO_ASM_FUNC |
| 882 |
| 883 void Bic(const VRegister& vd, const int imm8, const int left_shift = 0) { |
| 884 DCHECK(allow_macro_instructions_); |
| 885 bic(vd, imm8, left_shift); |
| 886 } |
| 887 void Cmeq(const VRegister& vd, const VRegister& vn, int imm) { |
| 888 DCHECK(allow_macro_instructions_); |
| 889 cmeq(vd, vn, imm); |
| 890 } |
| 891 void Cmge(const VRegister& vd, const VRegister& vn, int imm) { |
| 892 DCHECK(allow_macro_instructions_); |
| 893 cmge(vd, vn, imm); |
| 894 } |
| 895 void Cmgt(const VRegister& vd, const VRegister& vn, int imm) { |
| 896 DCHECK(allow_macro_instructions_); |
| 897 cmgt(vd, vn, imm); |
| 898 } |
| 899 void Cmle(const VRegister& vd, const VRegister& vn, int imm) { |
| 900 DCHECK(allow_macro_instructions_); |
| 901 cmle(vd, vn, imm); |
| 902 } |
| 903 void Cmlt(const VRegister& vd, const VRegister& vn, int imm) { |
| 904 DCHECK(allow_macro_instructions_); |
| 905 cmlt(vd, vn, imm); |
| 906 } |
| 907 // NEON by element instructions. |
| 908 #define NEON_BYELEMENT_MACRO_LIST(V) \ |
| 909 V(fmul, Fmul) \ |
| 910 V(fmla, Fmla) \ |
| 911 V(fmls, Fmls) \ |
| 912 V(fmulx, Fmulx) \ |
| 913 V(mul, Mul) \ |
| 914 V(mla, Mla) \ |
| 915 V(mls, Mls) \ |
| 916 V(sqdmulh, Sqdmulh) \ |
| 917 V(sqrdmulh, Sqrdmulh) \ |
| 918 V(sqdmull, Sqdmull) \ |
| 919 V(sqdmull2, Sqdmull2) \ |
| 920 V(sqdmlal, Sqdmlal) \ |
| 921 V(sqdmlal2, Sqdmlal2) \ |
| 922 V(sqdmlsl, Sqdmlsl) \ |
| 923 V(sqdmlsl2, Sqdmlsl2) \ |
| 924 V(smull, Smull) \ |
| 925 V(smull2, Smull2) \ |
| 926 V(smlal, Smlal) \ |
| 927 V(smlal2, Smlal2) \ |
| 928 V(smlsl, Smlsl) \ |
| 929 V(smlsl2, Smlsl2) \ |
| 930 V(umull, Umull) \ |
| 931 V(umull2, Umull2) \ |
| 932 V(umlal, Umlal) \ |
| 933 V(umlal2, Umlal2) \ |
| 934 V(umlsl, Umlsl) \ |
| 935 V(umlsl2, Umlsl2) |
| 936 |
| 937 #define DEFINE_MACRO_ASM_FUNC(ASM, MASM) \ |
| 938 void MASM(const VRegister& vd, const VRegister& vn, const VRegister& vm, \ |
| 939 int vm_index) { \ |
| 940 DCHECK(allow_macro_instructions_); \ |
| 941 ASM(vd, vn, vm, vm_index); \ |
| 942 } |
| 943 NEON_BYELEMENT_MACRO_LIST(DEFINE_MACRO_ASM_FUNC) |
| 944 #undef DEFINE_MACRO_ASM_FUNC |
| 945 |
| 946 #define NEON_2VREG_SHIFT_MACRO_LIST(V) \ |
| 947 V(rshrn, Rshrn) \ |
| 948 V(rshrn2, Rshrn2) \ |
| 949 V(shl, Shl) \ |
| 950 V(shll, Shll) \ |
| 951 V(shll2, Shll2) \ |
| 952 V(shrn, Shrn) \ |
| 953 V(shrn2, Shrn2) \ |
| 954 V(sli, Sli) \ |
| 955 V(sqrshrn, Sqrshrn) \ |
| 956 V(sqrshrn2, Sqrshrn2) \ |
| 957 V(sqrshrun, Sqrshrun) \ |
| 958 V(sqrshrun2, Sqrshrun2) \ |
| 959 V(sqshl, Sqshl) \ |
| 960 V(sqshlu, Sqshlu) \ |
| 961 V(sqshrn, Sqshrn) \ |
| 962 V(sqshrn2, Sqshrn2) \ |
| 963 V(sqshrun, Sqshrun) \ |
| 964 V(sqshrun2, Sqshrun2) \ |
| 965 V(sri, Sri) \ |
| 966 V(srshr, Srshr) \ |
| 967 V(srsra, Srsra) \ |
| 968 V(sshll, Sshll) \ |
| 969 V(sshll2, Sshll2) \ |
| 970 V(sshr, Sshr) \ |
| 971 V(ssra, Ssra) \ |
| 972 V(uqrshrn, Uqrshrn) \ |
| 973 V(uqrshrn2, Uqrshrn2) \ |
| 974 V(uqshl, Uqshl) \ |
| 975 V(uqshrn, Uqshrn) \ |
| 976 V(uqshrn2, Uqshrn2) \ |
| 977 V(urshr, Urshr) \ |
| 978 V(ursra, Ursra) \ |
| 979 V(ushll, Ushll) \ |
| 980 V(ushll2, Ushll2) \ |
| 981 V(ushr, Ushr) \ |
| 982 V(usra, Usra) |
| 983 |
| 984 #define DEFINE_MACRO_ASM_FUNC(ASM, MASM) \ |
| 985 void MASM(const VRegister& vd, const VRegister& vn, int shift) { \ |
| 986 DCHECK(allow_macro_instructions_); \ |
| 987 ASM(vd, vn, shift); \ |
| 988 } |
| 989 NEON_2VREG_SHIFT_MACRO_LIST(DEFINE_MACRO_ASM_FUNC) |
| 990 #undef DEFINE_MACRO_ASM_FUNC |
| 991 |
| 992 void Ld1(const VRegister& vt, const MemOperand& src) { |
| 993 DCHECK(allow_macro_instructions_); |
| 994 ld1(vt, src); |
| 995 } |
| 996 void Ld1(const VRegister& vt, const VRegister& vt2, const MemOperand& src) { |
| 997 DCHECK(allow_macro_instructions_); |
| 998 ld1(vt, vt2, src); |
| 999 } |
| 1000 void Ld1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, |
| 1001 const MemOperand& src) { |
| 1002 DCHECK(allow_macro_instructions_); |
| 1003 ld1(vt, vt2, vt3, src); |
| 1004 } |
| 1005 void Ld1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, |
| 1006 const VRegister& vt4, const MemOperand& src) { |
| 1007 DCHECK(allow_macro_instructions_); |
| 1008 ld1(vt, vt2, vt3, vt4, src); |
| 1009 } |
| 1010 void Ld1(const VRegister& vt, int lane, const MemOperand& src) { |
| 1011 DCHECK(allow_macro_instructions_); |
| 1012 ld1(vt, lane, src); |
| 1013 } |
| 1014 void Ld1r(const VRegister& vt, const MemOperand& src) { |
| 1015 DCHECK(allow_macro_instructions_); |
| 1016 ld1r(vt, src); |
| 1017 } |
| 1018 void Ld2(const VRegister& vt, const VRegister& vt2, const MemOperand& src) { |
| 1019 DCHECK(allow_macro_instructions_); |
| 1020 ld2(vt, vt2, src); |
| 1021 } |
| 1022 void Ld2(const VRegister& vt, const VRegister& vt2, int lane, |
| 1023 const MemOperand& src) { |
| 1024 DCHECK(allow_macro_instructions_); |
| 1025 ld2(vt, vt2, lane, src); |
| 1026 } |
| 1027 void Ld2r(const VRegister& vt, const VRegister& vt2, const MemOperand& src) { |
| 1028 DCHECK(allow_macro_instructions_); |
| 1029 ld2r(vt, vt2, src); |
| 1030 } |
| 1031 void Ld3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, |
| 1032 const MemOperand& src) { |
| 1033 DCHECK(allow_macro_instructions_); |
| 1034 ld3(vt, vt2, vt3, src); |
| 1035 } |
| 1036 void Ld3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, |
| 1037 int lane, const MemOperand& src) { |
| 1038 DCHECK(allow_macro_instructions_); |
| 1039 ld3(vt, vt2, vt3, lane, src); |
| 1040 } |
| 1041 void Ld3r(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, |
| 1042 const MemOperand& src) { |
| 1043 DCHECK(allow_macro_instructions_); |
| 1044 ld3r(vt, vt2, vt3, src); |
| 1045 } |
| 1046 void Ld4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, |
| 1047 const VRegister& vt4, const MemOperand& src) { |
| 1048 DCHECK(allow_macro_instructions_); |
| 1049 ld4(vt, vt2, vt3, vt4, src); |
| 1050 } |
| 1051 void Ld4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, |
| 1052 const VRegister& vt4, int lane, const MemOperand& src) { |
| 1053 DCHECK(allow_macro_instructions_); |
| 1054 ld4(vt, vt2, vt3, vt4, lane, src); |
| 1055 } |
| 1056 void Ld4r(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, |
| 1057 const VRegister& vt4, const MemOperand& src) { |
| 1058 DCHECK(allow_macro_instructions_); |
| 1059 ld4r(vt, vt2, vt3, vt4, src); |
| 1060 } |
| 1061 void St1(const VRegister& vt, const MemOperand& dst) { |
| 1062 DCHECK(allow_macro_instructions_); |
| 1063 st1(vt, dst); |
| 1064 } |
| 1065 void St1(const VRegister& vt, const VRegister& vt2, const MemOperand& dst) { |
| 1066 DCHECK(allow_macro_instructions_); |
| 1067 st1(vt, vt2, dst); |
| 1068 } |
| 1069 void St1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, |
| 1070 const MemOperand& dst) { |
| 1071 DCHECK(allow_macro_instructions_); |
| 1072 st1(vt, vt2, vt3, dst); |
| 1073 } |
| 1074 void St1(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, |
| 1075 const VRegister& vt4, const MemOperand& dst) { |
| 1076 DCHECK(allow_macro_instructions_); |
| 1077 st1(vt, vt2, vt3, vt4, dst); |
| 1078 } |
| 1079 void St1(const VRegister& vt, int lane, const MemOperand& dst) { |
| 1080 DCHECK(allow_macro_instructions_); |
| 1081 st1(vt, lane, dst); |
| 1082 } |
| 1083 void St2(const VRegister& vt, const VRegister& vt2, const MemOperand& dst) { |
| 1084 DCHECK(allow_macro_instructions_); |
| 1085 st2(vt, vt2, dst); |
| 1086 } |
| 1087 void St3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, |
| 1088 const MemOperand& dst) { |
| 1089 DCHECK(allow_macro_instructions_); |
| 1090 st3(vt, vt2, vt3, dst); |
| 1091 } |
| 1092 void St4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, |
| 1093 const VRegister& vt4, const MemOperand& dst) { |
| 1094 DCHECK(allow_macro_instructions_); |
| 1095 st4(vt, vt2, vt3, vt4, dst); |
| 1096 } |
| 1097 void St2(const VRegister& vt, const VRegister& vt2, int lane, |
| 1098 const MemOperand& dst) { |
| 1099 DCHECK(allow_macro_instructions_); |
| 1100 st2(vt, vt2, lane, dst); |
| 1101 } |
| 1102 void St3(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, |
| 1103 int lane, const MemOperand& dst) { |
| 1104 DCHECK(allow_macro_instructions_); |
| 1105 st3(vt, vt2, vt3, lane, dst); |
| 1106 } |
| 1107 void St4(const VRegister& vt, const VRegister& vt2, const VRegister& vt3, |
| 1108 const VRegister& vt4, int lane, const MemOperand& dst) { |
| 1109 DCHECK(allow_macro_instructions_); |
| 1110 st4(vt, vt2, vt3, vt4, lane, dst); |
| 1111 } |
| 1112 void Tbl(const VRegister& vd, const VRegister& vn, const VRegister& vm) { |
| 1113 DCHECK(allow_macro_instructions_); |
| 1114 tbl(vd, vn, vm); |
| 1115 } |
| 1116 void Tbl(const VRegister& vd, const VRegister& vn, const VRegister& vn2, |
| 1117 const VRegister& vm) { |
| 1118 DCHECK(allow_macro_instructions_); |
| 1119 tbl(vd, vn, vn2, vm); |
| 1120 } |
| 1121 void Tbl(const VRegister& vd, const VRegister& vn, const VRegister& vn2, |
| 1122 const VRegister& vn3, const VRegister& vm) { |
| 1123 DCHECK(allow_macro_instructions_); |
| 1124 tbl(vd, vn, vn2, vn3, vm); |
| 1125 } |
| 1126 void Tbl(const VRegister& vd, const VRegister& vn, const VRegister& vn2, |
| 1127 const VRegister& vn3, const VRegister& vn4, const VRegister& vm) { |
| 1128 DCHECK(allow_macro_instructions_); |
| 1129 tbl(vd, vn, vn2, vn3, vn4, vm); |
| 1130 } |
| 1131 void Tbx(const VRegister& vd, const VRegister& vn, const VRegister& vm) { |
| 1132 DCHECK(allow_macro_instructions_); |
| 1133 tbx(vd, vn, vm); |
| 1134 } |
| 1135 void Tbx(const VRegister& vd, const VRegister& vn, const VRegister& vn2, |
| 1136 const VRegister& vm) { |
| 1137 DCHECK(allow_macro_instructions_); |
| 1138 tbx(vd, vn, vn2, vm); |
| 1139 } |
| 1140 void Tbx(const VRegister& vd, const VRegister& vn, const VRegister& vn2, |
| 1141 const VRegister& vn3, const VRegister& vm) { |
| 1142 DCHECK(allow_macro_instructions_); |
| 1143 tbx(vd, vn, vn2, vn3, vm); |
| 1144 } |
| 1145 void Tbx(const VRegister& vd, const VRegister& vn, const VRegister& vn2, |
| 1146 const VRegister& vn3, const VRegister& vn4, const VRegister& vm) { |
| 1147 DCHECK(allow_macro_instructions_); |
| 1148 tbx(vd, vn, vn2, vn3, vn4, vm); |
| 1149 } |
| 1150 |
576 // Pseudo-instructions ------------------------------------------------------ | 1151 // Pseudo-instructions ------------------------------------------------------ |
577 | 1152 |
578 // Compute rd = abs(rm). | 1153 // Compute rd = abs(rm). |
579 // This function clobbers the condition flags. On output the overflow flag is | 1154 // This function clobbers the condition flags. On output the overflow flag is |
580 // set iff the negation overflowed. | 1155 // set iff the negation overflowed. |
581 // | 1156 // |
582 // If rm is the minimum representable value, the result is not representable. | 1157 // If rm is the minimum representable value, the result is not representable. |
583 // Handlers for each case can be specified using the relevant labels. | 1158 // Handlers for each case can be specified using the relevant labels. |
584 void Abs(const Register& rd, const Register& rm, | 1159 void Abs(const Register& rd, const Register& rm, |
585 Label * is_not_representable = NULL, | 1160 Label * is_not_representable = NULL, |
(...skipping 30 matching lines...) Expand all Loading... |
616 void Push(const CPURegister& src0, const CPURegister& src1, | 1191 void Push(const CPURegister& src0, const CPURegister& src1, |
617 const CPURegister& src2, const CPURegister& src3, | 1192 const CPURegister& src2, const CPURegister& src3, |
618 const CPURegister& src4, const CPURegister& src5 = NoReg, | 1193 const CPURegister& src4, const CPURegister& src5 = NoReg, |
619 const CPURegister& src6 = NoReg, const CPURegister& src7 = NoReg); | 1194 const CPURegister& src6 = NoReg, const CPURegister& src7 = NoReg); |
620 void Pop(const CPURegister& dst0, const CPURegister& dst1 = NoReg, | 1195 void Pop(const CPURegister& dst0, const CPURegister& dst1 = NoReg, |
621 const CPURegister& dst2 = NoReg, const CPURegister& dst3 = NoReg); | 1196 const CPURegister& dst2 = NoReg, const CPURegister& dst3 = NoReg); |
622 void Pop(const CPURegister& dst0, const CPURegister& dst1, | 1197 void Pop(const CPURegister& dst0, const CPURegister& dst1, |
623 const CPURegister& dst2, const CPURegister& dst3, | 1198 const CPURegister& dst2, const CPURegister& dst3, |
624 const CPURegister& dst4, const CPURegister& dst5 = NoReg, | 1199 const CPURegister& dst4, const CPURegister& dst5 = NoReg, |
625 const CPURegister& dst6 = NoReg, const CPURegister& dst7 = NoReg); | 1200 const CPURegister& dst6 = NoReg, const CPURegister& dst7 = NoReg); |
626 void Push(const Register& src0, const FPRegister& src1); | 1201 void Push(const Register& src0, const VRegister& src1); |
627 | 1202 |
628 // Alternative forms of Push and Pop, taking a RegList or CPURegList that | 1203 // Alternative forms of Push and Pop, taking a RegList or CPURegList that |
629 // specifies the registers that are to be pushed or popped. Higher-numbered | 1204 // specifies the registers that are to be pushed or popped. Higher-numbered |
630 // registers are associated with higher memory addresses (as in the A32 push | 1205 // registers are associated with higher memory addresses (as in the A32 push |
631 // and pop instructions). | 1206 // and pop instructions). |
632 // | 1207 // |
633 // (Push|Pop)SizeRegList allow you to specify the register size as a | 1208 // (Push|Pop)SizeRegList allow you to specify the register size as a |
634 // parameter. Only kXRegSizeInBits, kWRegSizeInBits, kDRegSizeInBits and | 1209 // parameter. Only kXRegSizeInBits, kWRegSizeInBits, kDRegSizeInBits and |
635 // kSRegSizeInBits are supported. | 1210 // kSRegSizeInBits are supported. |
636 // | 1211 // |
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652 inline void PopXRegList(RegList regs) { | 1227 inline void PopXRegList(RegList regs) { |
653 PopSizeRegList(regs, kXRegSizeInBits); | 1228 PopSizeRegList(regs, kXRegSizeInBits); |
654 } | 1229 } |
655 inline void PushWRegList(RegList regs) { | 1230 inline void PushWRegList(RegList regs) { |
656 PushSizeRegList(regs, kWRegSizeInBits); | 1231 PushSizeRegList(regs, kWRegSizeInBits); |
657 } | 1232 } |
658 inline void PopWRegList(RegList regs) { | 1233 inline void PopWRegList(RegList regs) { |
659 PopSizeRegList(regs, kWRegSizeInBits); | 1234 PopSizeRegList(regs, kWRegSizeInBits); |
660 } | 1235 } |
661 inline void PushDRegList(RegList regs) { | 1236 inline void PushDRegList(RegList regs) { |
662 PushSizeRegList(regs, kDRegSizeInBits, CPURegister::kFPRegister); | 1237 PushSizeRegList(regs, kDRegSizeInBits, CPURegister::kVRegister); |
663 } | 1238 } |
664 inline void PopDRegList(RegList regs) { | 1239 inline void PopDRegList(RegList regs) { |
665 PopSizeRegList(regs, kDRegSizeInBits, CPURegister::kFPRegister); | 1240 PopSizeRegList(regs, kDRegSizeInBits, CPURegister::kVRegister); |
666 } | 1241 } |
667 inline void PushSRegList(RegList regs) { | 1242 inline void PushSRegList(RegList regs) { |
668 PushSizeRegList(regs, kSRegSizeInBits, CPURegister::kFPRegister); | 1243 PushSizeRegList(regs, kSRegSizeInBits, CPURegister::kVRegister); |
669 } | 1244 } |
670 inline void PopSRegList(RegList regs) { | 1245 inline void PopSRegList(RegList regs) { |
671 PopSizeRegList(regs, kSRegSizeInBits, CPURegister::kFPRegister); | 1246 PopSizeRegList(regs, kSRegSizeInBits, CPURegister::kVRegister); |
672 } | 1247 } |
673 | 1248 |
674 // Push the specified register 'count' times. | 1249 // Push the specified register 'count' times. |
675 void PushMultipleTimes(CPURegister src, Register count); | 1250 void PushMultipleTimes(CPURegister src, Register count); |
676 void PushMultipleTimes(CPURegister src, int count); | 1251 void PushMultipleTimes(CPURegister src, int count); |
677 | 1252 |
678 // This is a convenience method for pushing a single Handle<Object>. | 1253 // This is a convenience method for pushing a single Handle<Object>. |
679 inline void Push(Handle<Object> handle); | 1254 inline void Push(Handle<Object> handle); |
680 inline void Push(Smi* smi); | 1255 inline void Push(Smi* smi); |
681 | 1256 |
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897 // | 1472 // |
898 // This method asserts that StackPointer() is not csp, since the call does | 1473 // This method asserts that StackPointer() is not csp, since the call does |
899 // not make sense in that context. | 1474 // not make sense in that context. |
900 inline void SyncSystemStackPointer(); | 1475 inline void SyncSystemStackPointer(); |
901 | 1476 |
902 // Helpers ------------------------------------------------------------------ | 1477 // Helpers ------------------------------------------------------------------ |
903 // Root register. | 1478 // Root register. |
904 inline void InitializeRootRegister(); | 1479 inline void InitializeRootRegister(); |
905 | 1480 |
906 void AssertFPCRState(Register fpcr = NoReg); | 1481 void AssertFPCRState(Register fpcr = NoReg); |
907 void CanonicalizeNaN(const FPRegister& dst, const FPRegister& src); | 1482 void CanonicalizeNaN(const VRegister& dst, const VRegister& src); |
908 void CanonicalizeNaN(const FPRegister& reg) { | 1483 void CanonicalizeNaN(const VRegister& reg) { CanonicalizeNaN(reg, reg); } |
909 CanonicalizeNaN(reg, reg); | |
910 } | |
911 | 1484 |
912 // Load an object from the root table. | 1485 // Load an object from the root table. |
913 void LoadRoot(CPURegister destination, | 1486 void LoadRoot(CPURegister destination, |
914 Heap::RootListIndex index); | 1487 Heap::RootListIndex index); |
915 // Store an object to the root table. | 1488 // Store an object to the root table. |
916 void StoreRoot(Register source, | 1489 void StoreRoot(Register source, |
917 Heap::RootListIndex index); | 1490 Heap::RootListIndex index); |
918 | 1491 |
919 // Load both TrueValue and FalseValue roots. | 1492 // Load both TrueValue and FalseValue roots. |
920 void LoadTrueFalseRoots(Register true_root, Register false_root); | 1493 void LoadTrueFalseRoots(Register true_root, Register false_root); |
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950 void DecodeField(Register reg) { | 1523 void DecodeField(Register reg) { |
951 DecodeField<Field>(reg, reg); | 1524 DecodeField<Field>(reg, reg); |
952 } | 1525 } |
953 | 1526 |
954 // ---- SMI and Number Utilities ---- | 1527 // ---- SMI and Number Utilities ---- |
955 | 1528 |
956 inline void SmiTag(Register dst, Register src); | 1529 inline void SmiTag(Register dst, Register src); |
957 inline void SmiTag(Register smi); | 1530 inline void SmiTag(Register smi); |
958 inline void SmiUntag(Register dst, Register src); | 1531 inline void SmiUntag(Register dst, Register src); |
959 inline void SmiUntag(Register smi); | 1532 inline void SmiUntag(Register smi); |
960 inline void SmiUntagToDouble(FPRegister dst, | 1533 inline void SmiUntagToDouble(VRegister dst, Register src, |
961 Register src, | |
962 UntagMode mode = kNotSpeculativeUntag); | 1534 UntagMode mode = kNotSpeculativeUntag); |
963 inline void SmiUntagToFloat(FPRegister dst, | 1535 inline void SmiUntagToFloat(VRegister dst, Register src, |
964 Register src, | |
965 UntagMode mode = kNotSpeculativeUntag); | 1536 UntagMode mode = kNotSpeculativeUntag); |
966 | 1537 |
967 // Tag and push in one step. | 1538 // Tag and push in one step. |
968 inline void SmiTagAndPush(Register src); | 1539 inline void SmiTagAndPush(Register src); |
969 inline void SmiTagAndPush(Register src1, Register src2); | 1540 inline void SmiTagAndPush(Register src1, Register src2); |
970 | 1541 |
971 inline void JumpIfSmi(Register value, | 1542 inline void JumpIfSmi(Register value, |
972 Label* smi_label, | 1543 Label* smi_label, |
973 Label* not_smi_label = NULL); | 1544 Label* not_smi_label = NULL); |
974 inline void JumpIfNotSmi(Register value, Label* not_smi_label); | 1545 inline void JumpIfNotSmi(Register value, Label* not_smi_label); |
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1036 // Saturate a double in input to an unsigned 8-bit integer in output. | 1607 // Saturate a double in input to an unsigned 8-bit integer in output. |
1037 void ClampDoubleToUint8(Register output, | 1608 void ClampDoubleToUint8(Register output, |
1038 DoubleRegister input, | 1609 DoubleRegister input, |
1039 DoubleRegister dbl_scratch); | 1610 DoubleRegister dbl_scratch); |
1040 | 1611 |
1041 // Try to represent a double as a signed 32-bit int. | 1612 // Try to represent a double as a signed 32-bit int. |
1042 // This succeeds if the result compares equal to the input, so inputs of -0.0 | 1613 // This succeeds if the result compares equal to the input, so inputs of -0.0 |
1043 // are represented as 0 and handled as a success. | 1614 // are represented as 0 and handled as a success. |
1044 // | 1615 // |
1045 // On output the Z flag is set if the operation was successful. | 1616 // On output the Z flag is set if the operation was successful. |
1046 void TryRepresentDoubleAsInt32(Register as_int, | 1617 void TryRepresentDoubleAsInt32(Register as_int, VRegister value, |
1047 FPRegister value, | 1618 VRegister scratch_d, |
1048 FPRegister scratch_d, | |
1049 Label* on_successful_conversion = NULL, | 1619 Label* on_successful_conversion = NULL, |
1050 Label* on_failed_conversion = NULL) { | 1620 Label* on_failed_conversion = NULL) { |
1051 DCHECK(as_int.Is32Bits()); | 1621 DCHECK(as_int.Is32Bits()); |
1052 TryRepresentDoubleAsInt(as_int, value, scratch_d, on_successful_conversion, | 1622 TryRepresentDoubleAsInt(as_int, value, scratch_d, on_successful_conversion, |
1053 on_failed_conversion); | 1623 on_failed_conversion); |
1054 } | 1624 } |
1055 | 1625 |
1056 // Try to represent a double as a signed 64-bit int. | 1626 // Try to represent a double as a signed 64-bit int. |
1057 // This succeeds if the result compares equal to the input, so inputs of -0.0 | 1627 // This succeeds if the result compares equal to the input, so inputs of -0.0 |
1058 // are represented as 0 and handled as a success. | 1628 // are represented as 0 and handled as a success. |
1059 // | 1629 // |
1060 // On output the Z flag is set if the operation was successful. | 1630 // On output the Z flag is set if the operation was successful. |
1061 void TryRepresentDoubleAsInt64(Register as_int, | 1631 void TryRepresentDoubleAsInt64(Register as_int, VRegister value, |
1062 FPRegister value, | 1632 VRegister scratch_d, |
1063 FPRegister scratch_d, | |
1064 Label* on_successful_conversion = NULL, | 1633 Label* on_successful_conversion = NULL, |
1065 Label* on_failed_conversion = NULL) { | 1634 Label* on_failed_conversion = NULL) { |
1066 DCHECK(as_int.Is64Bits()); | 1635 DCHECK(as_int.Is64Bits()); |
1067 TryRepresentDoubleAsInt(as_int, value, scratch_d, on_successful_conversion, | 1636 TryRepresentDoubleAsInt(as_int, value, scratch_d, on_successful_conversion, |
1068 on_failed_conversion); | 1637 on_failed_conversion); |
1069 } | 1638 } |
1070 | 1639 |
1071 // ---- Object Utilities ---- | 1640 // ---- Object Utilities ---- |
1072 | 1641 |
1073 // Initialize fields with filler values. Fields starting at |current_address| | 1642 // Initialize fields with filler values. Fields starting at |current_address| |
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1316 Register scratch, AllocationFlags flags); | 1885 Register scratch, AllocationFlags flags); |
1317 | 1886 |
1318 void FastAllocate(int object_size, Register result, Register scratch1, | 1887 void FastAllocate(int object_size, Register result, Register scratch1, |
1319 Register scratch2, AllocationFlags flags); | 1888 Register scratch2, AllocationFlags flags); |
1320 | 1889 |
1321 // Allocates a heap number or jumps to the gc_required label if the young | 1890 // Allocates a heap number or jumps to the gc_required label if the young |
1322 // space is full and a scavenge is needed. | 1891 // space is full and a scavenge is needed. |
1323 // All registers are clobbered. | 1892 // All registers are clobbered. |
1324 // If no heap_number_map register is provided, the function will take care of | 1893 // If no heap_number_map register is provided, the function will take care of |
1325 // loading it. | 1894 // loading it. |
1326 void AllocateHeapNumber(Register result, | 1895 void AllocateHeapNumber(Register result, Label* gc_required, |
1327 Label* gc_required, | 1896 Register scratch1, Register scratch2, |
1328 Register scratch1, | 1897 CPURegister value = NoVReg, |
1329 Register scratch2, | |
1330 CPURegister value = NoFPReg, | |
1331 CPURegister heap_number_map = NoReg, | 1898 CPURegister heap_number_map = NoReg, |
1332 MutableMode mode = IMMUTABLE); | 1899 MutableMode mode = IMMUTABLE); |
1333 | 1900 |
1334 // Allocate and initialize a JSValue wrapper with the specified {constructor} | 1901 // Allocate and initialize a JSValue wrapper with the specified {constructor} |
1335 // and {value}. | 1902 // and {value}. |
1336 void AllocateJSValue(Register result, Register constructor, Register value, | 1903 void AllocateJSValue(Register result, Register constructor, Register value, |
1337 Register scratch1, Register scratch2, | 1904 Register scratch1, Register scratch2, |
1338 Label* gc_required); | 1905 Label* gc_required); |
1339 | 1906 |
1340 // --------------------------------------------------------------------------- | 1907 // --------------------------------------------------------------------------- |
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1793 | 2360 |
1794 CPURegList* TmpList() { return &tmp_list_; } | 2361 CPURegList* TmpList() { return &tmp_list_; } |
1795 CPURegList* FPTmpList() { return &fptmp_list_; } | 2362 CPURegList* FPTmpList() { return &fptmp_list_; } |
1796 | 2363 |
1797 static CPURegList DefaultTmpList(); | 2364 static CPURegList DefaultTmpList(); |
1798 static CPURegList DefaultFPTmpList(); | 2365 static CPURegList DefaultFPTmpList(); |
1799 | 2366 |
1800 // Like printf, but print at run-time from generated code. | 2367 // Like printf, but print at run-time from generated code. |
1801 // | 2368 // |
1802 // The caller must ensure that arguments for floating-point placeholders | 2369 // The caller must ensure that arguments for floating-point placeholders |
1803 // (such as %e, %f or %g) are FPRegisters, and that arguments for integer | 2370 // (such as %e, %f or %g) are VRegisters, and that arguments for integer |
1804 // placeholders are Registers. | 2371 // placeholders are Registers. |
1805 // | 2372 // |
1806 // At the moment it is only possible to print the value of csp if it is the | 2373 // At the moment it is only possible to print the value of csp if it is the |
1807 // current stack pointer. Otherwise, the MacroAssembler will automatically | 2374 // current stack pointer. Otherwise, the MacroAssembler will automatically |
1808 // update csp on every push (using BumpSystemStackPointer), so determining its | 2375 // update csp on every push (using BumpSystemStackPointer), so determining its |
1809 // value is difficult. | 2376 // value is difficult. |
1810 // | 2377 // |
1811 // Format placeholders that refer to more than one argument, or to a specific | 2378 // Format placeholders that refer to more than one argument, or to a specific |
1812 // argument, are not supported. This includes formats like "%1$d" or "%.*d". | 2379 // argument, are not supported. This includes formats like "%1$d" or "%.*d". |
1813 // | 2380 // |
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1887 // block of registers. | 2454 // block of registers. |
1888 // | 2455 // |
1889 // Note that size is per register, and is specified in bytes. | 2456 // Note that size is per register, and is specified in bytes. |
1890 void PushHelper(int count, int size, | 2457 void PushHelper(int count, int size, |
1891 const CPURegister& src0, const CPURegister& src1, | 2458 const CPURegister& src0, const CPURegister& src1, |
1892 const CPURegister& src2, const CPURegister& src3); | 2459 const CPURegister& src2, const CPURegister& src3); |
1893 void PopHelper(int count, int size, | 2460 void PopHelper(int count, int size, |
1894 const CPURegister& dst0, const CPURegister& dst1, | 2461 const CPURegister& dst0, const CPURegister& dst1, |
1895 const CPURegister& dst2, const CPURegister& dst3); | 2462 const CPURegister& dst2, const CPURegister& dst3); |
1896 | 2463 |
| 2464 void Movi16bitHelper(const VRegister& vd, uint64_t imm); |
| 2465 void Movi32bitHelper(const VRegister& vd, uint64_t imm); |
| 2466 void Movi64bitHelper(const VRegister& vd, uint64_t imm); |
| 2467 |
1897 // Call Printf. On a native build, a simple call will be generated, but if the | 2468 // Call Printf. On a native build, a simple call will be generated, but if the |
1898 // simulator is being used then a suitable pseudo-instruction is used. The | 2469 // simulator is being used then a suitable pseudo-instruction is used. The |
1899 // arguments and stack (csp) must be prepared by the caller as for a normal | 2470 // arguments and stack (csp) must be prepared by the caller as for a normal |
1900 // AAPCS64 call to 'printf'. | 2471 // AAPCS64 call to 'printf'. |
1901 // | 2472 // |
1902 // The 'args' argument should point to an array of variable arguments in their | 2473 // The 'args' argument should point to an array of variable arguments in their |
1903 // proper PCS registers (and in calling order). The argument registers can | 2474 // proper PCS registers (and in calling order). The argument registers can |
1904 // have mixed types. The format string (x0) should not be included. | 2475 // have mixed types. The format string (x0) should not be included. |
1905 void CallPrintf(int arg_count = 0, const CPURegister * args = NULL); | 2476 void CallPrintf(int arg_count = 0, const CPURegister * args = NULL); |
1906 | 2477 |
1907 // Helper for implementing JumpIfNotInNewSpace and JumpIfInNewSpace. | 2478 // Helper for implementing JumpIfNotInNewSpace and JumpIfInNewSpace. |
1908 void InNewSpace(Register object, | 2479 void InNewSpace(Register object, |
1909 Condition cond, // eq for new space, ne otherwise. | 2480 Condition cond, // eq for new space, ne otherwise. |
1910 Label* branch); | 2481 Label* branch); |
1911 | 2482 |
1912 // Try to represent a double as an int so that integer fast-paths may be | 2483 // Try to represent a double as an int so that integer fast-paths may be |
1913 // used. Not every valid integer value is guaranteed to be caught. | 2484 // used. Not every valid integer value is guaranteed to be caught. |
1914 // It supports both 32-bit and 64-bit integers depending whether 'as_int' | 2485 // It supports both 32-bit and 64-bit integers depending whether 'as_int' |
1915 // is a W or X register. | 2486 // is a W or X register. |
1916 // | 2487 // |
1917 // This does not distinguish between +0 and -0, so if this distinction is | 2488 // This does not distinguish between +0 and -0, so if this distinction is |
1918 // important it must be checked separately. | 2489 // important it must be checked separately. |
1919 // | 2490 // |
1920 // On output the Z flag is set if the operation was successful. | 2491 // On output the Z flag is set if the operation was successful. |
1921 void TryRepresentDoubleAsInt(Register as_int, | 2492 void TryRepresentDoubleAsInt(Register as_int, VRegister value, |
1922 FPRegister value, | 2493 VRegister scratch_d, |
1923 FPRegister scratch_d, | |
1924 Label* on_successful_conversion = NULL, | 2494 Label* on_successful_conversion = NULL, |
1925 Label* on_failed_conversion = NULL); | 2495 Label* on_failed_conversion = NULL); |
1926 | 2496 |
1927 bool generating_stub_; | 2497 bool generating_stub_; |
1928 #if DEBUG | 2498 #if DEBUG |
1929 // Tell whether any of the macro instruction can be used. When false the | 2499 // Tell whether any of the macro instruction can be used. When false the |
1930 // MacroAssembler will assert if a method which can emit a variable number | 2500 // MacroAssembler will assert if a method which can emit a variable number |
1931 // of instructions is called. | 2501 // of instructions is called. |
1932 bool allow_macro_instructions_; | 2502 bool allow_macro_instructions_; |
1933 #endif | 2503 #endif |
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2033 // | 2603 // |
2034 // When the scope ends, the MacroAssembler's lists will be restored to their | 2604 // When the scope ends, the MacroAssembler's lists will be restored to their |
2035 // original state, even if the lists were modified by some other means. | 2605 // original state, even if the lists were modified by some other means. |
2036 class UseScratchRegisterScope { | 2606 class UseScratchRegisterScope { |
2037 public: | 2607 public: |
2038 explicit UseScratchRegisterScope(MacroAssembler* masm) | 2608 explicit UseScratchRegisterScope(MacroAssembler* masm) |
2039 : available_(masm->TmpList()), | 2609 : available_(masm->TmpList()), |
2040 availablefp_(masm->FPTmpList()), | 2610 availablefp_(masm->FPTmpList()), |
2041 old_available_(available_->list()), | 2611 old_available_(available_->list()), |
2042 old_availablefp_(availablefp_->list()) { | 2612 old_availablefp_(availablefp_->list()) { |
2043 DCHECK(available_->type() == CPURegister::kRegister); | 2613 DCHECK_EQ(available_->type(), CPURegister::kRegister); |
2044 DCHECK(availablefp_->type() == CPURegister::kFPRegister); | 2614 DCHECK_EQ(availablefp_->type(), CPURegister::kVRegister); |
2045 } | 2615 } |
2046 | 2616 |
2047 ~UseScratchRegisterScope(); | 2617 ~UseScratchRegisterScope(); |
2048 | 2618 |
2049 // Take a register from the appropriate temps list. It will be returned | 2619 // Take a register from the appropriate temps list. It will be returned |
2050 // automatically when the scope ends. | 2620 // automatically when the scope ends. |
2051 Register AcquireW() { return AcquireNextAvailable(available_).W(); } | 2621 Register AcquireW() { return AcquireNextAvailable(available_).W(); } |
2052 Register AcquireX() { return AcquireNextAvailable(available_).X(); } | 2622 Register AcquireX() { return AcquireNextAvailable(available_).X(); } |
2053 FPRegister AcquireS() { return AcquireNextAvailable(availablefp_).S(); } | 2623 VRegister AcquireS() { return AcquireNextAvailable(availablefp_).S(); } |
2054 FPRegister AcquireD() { return AcquireNextAvailable(availablefp_).D(); } | 2624 VRegister AcquireD() { return AcquireNextAvailable(availablefp_).D(); } |
2055 | 2625 |
2056 Register UnsafeAcquire(const Register& reg) { | 2626 Register UnsafeAcquire(const Register& reg) { |
2057 return Register(UnsafeAcquire(available_, reg)); | 2627 return Register(UnsafeAcquire(available_, reg)); |
2058 } | 2628 } |
2059 | 2629 |
2060 Register AcquireSameSizeAs(const Register& reg); | 2630 Register AcquireSameSizeAs(const Register& reg); |
2061 FPRegister AcquireSameSizeAs(const FPRegister& reg); | 2631 VRegister AcquireSameSizeAs(const VRegister& reg); |
2062 | 2632 |
2063 private: | 2633 private: |
2064 static CPURegister AcquireNextAvailable(CPURegList* available); | 2634 static CPURegister AcquireNextAvailable(CPURegList* available); |
2065 static CPURegister UnsafeAcquire(CPURegList* available, | 2635 static CPURegister UnsafeAcquire(CPURegList* available, |
2066 const CPURegister& reg); | 2636 const CPURegister& reg); |
2067 | 2637 |
2068 // Available scratch registers. | 2638 // Available scratch registers. |
2069 CPURegList* available_; // kRegister | 2639 CPURegList* available_; // kRegister |
2070 CPURegList* availablefp_; // kFPRegister | 2640 CPURegList* availablefp_; // kVRegister |
2071 | 2641 |
2072 // The state of the available lists at the start of this scope. | 2642 // The state of the available lists at the start of this scope. |
2073 RegList old_available_; // kRegister | 2643 RegList old_available_; // kRegister |
2074 RegList old_availablefp_; // kFPRegister | 2644 RegList old_availablefp_; // kVRegister |
2075 }; | 2645 }; |
2076 | 2646 |
2077 MemOperand ContextMemOperand(Register context, int index = 0); | 2647 MemOperand ContextMemOperand(Register context, int index = 0); |
2078 MemOperand NativeContextMemOperand(); | 2648 MemOperand NativeContextMemOperand(); |
2079 | 2649 |
2080 // Encode and decode information about patchable inline SMI checks. | 2650 // Encode and decode information about patchable inline SMI checks. |
2081 class InlineSmiCheckInfo { | 2651 class InlineSmiCheckInfo { |
2082 public: | 2652 public: |
2083 explicit InlineSmiCheckInfo(Address info); | 2653 explicit InlineSmiCheckInfo(Address info); |
2084 | 2654 |
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2127 class RegisterBits : public BitField<unsigned, 0, 5> {}; | 2697 class RegisterBits : public BitField<unsigned, 0, 5> {}; |
2128 class DeltaBits : public BitField<uint32_t, 5, 32-5> {}; | 2698 class DeltaBits : public BitField<uint32_t, 5, 32-5> {}; |
2129 }; | 2699 }; |
2130 | 2700 |
2131 } // namespace internal | 2701 } // namespace internal |
2132 } // namespace v8 | 2702 } // namespace v8 |
2133 | 2703 |
2134 #define ACCESS_MASM(masm) masm-> | 2704 #define ACCESS_MASM(masm) masm-> |
2135 | 2705 |
2136 #endif // V8_ARM64_MACRO_ASSEMBLER_ARM64_H_ | 2706 #endif // V8_ARM64_MACRO_ASSEMBLER_ARM64_H_ |
OLD | NEW |