| Index: src/arm/disasm-arm.cc
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| diff --git a/src/arm/disasm-arm.cc b/src/arm/disasm-arm.cc
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| index c9e7b1844b9028730043f74d6f98f43b542041d1..225cd7b41197163c5a4bb2d2885d216619e9889c 100644
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| --- a/src/arm/disasm-arm.cc
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| +++ b/src/arm/disasm-arm.cc
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| @@ -1950,6 +1950,13 @@ void Decoder::DecodeSpecialCondition(Instruction* instr) {
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|                         op, size, Vd, Vn, Vm);
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|            break;
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|          }
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| +        case 0xb: {
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| +          // vpadd.i<size> Dd, Dm, Dn.
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| +          out_buffer_pos_ +=
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| +              SNPrintF(out_buffer_ + out_buffer_pos_, "vpadd.i%d d%d, d%d, d%d",
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| +                       size, Vd, Vn, Vm);
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| +          break;
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| +        }
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|          case 0xd: {
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|            if (instr->Bit(4) == 0) {
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|              const char* op = (instr->Bits(21, 20) == 0) ? "vadd" : "vsub";
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| @@ -2130,10 +2137,16 @@ void Decoder::DecodeSpecialCondition(Instruction* instr) {
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|            break;
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|          }
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|          case 0xd: {
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| -          if (instr->Bit(21) == 0 && instr->Bit(6) == 1 && instr->Bit(4) == 1) {
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| -            // vmul.f32 Qd, Qn, Qm
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| +          if (instr->Bits(21, 20) == 0 && instr->Bit(6) == 1 &&
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| +              instr->Bit(4) == 1) {
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| +            // vmul.f32 Qd, Qm, Qn
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|              out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
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|                                          "vmul.f32 q%d, q%d, q%d", Vd, Vn, Vm);
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| +          } else if (instr->Bits(21, 20) == 0 && instr->Bit(6) == 0 &&
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| +                     instr->Bit(4) == 0) {
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| +            // vpadd.f32 Dd, Dm, Dn.
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| +            out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
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| +                                        "vpadd.f32 d%d, d%d, d%d", Vd, Vn, Vm);
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|            } else {
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|              Unknown(instr);
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|            }
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| 
 |