[WASM SIMD] Implement horizontal add for float and integer types.

src/arm/disasm-arm.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 // A Disassembler object is used to disassemble a block of code instruction by
 // instruction. The default implementation of the NameConverter object can be
 // overriden to modify register names or to do symbol lookup on addresses.
 //
 // The example below will disassemble a block of code and print it to stdout.
 //
@@ skipping 1932 matching lines @@
           break;
         }
         case 0xa: {
           // vpmin/vpmax.s<size> Dd, Dm, Dn.
           const char* op = instr->Bit(4) == 1 ? "vpmin" : "vpmax";
           out_buffer_pos_ +=
               SNPrintF(out_buffer_ + out_buffer_pos_, "%s.s%d d%d, d%d, d%d",
                        op, size, Vd, Vn, Vm);
           break;
         }
+        case 0xb: {
+          // vpadd.i<size> Dd, Dm, Dn.
+          out_buffer_pos_ +=
+              SNPrintF(out_buffer_ + out_buffer_pos_, "vpadd.i%d d%d, d%d, d%d",
+                       size, Vd, Vn, Vm);
+          break;
+        }
         case 0xd: {
           if (instr->Bit(4) == 0) {
             const char* op = (instr->Bits(21, 20) == 0) ? "vadd" : "vsub";
             // vadd/vsub.f32 Qd, Qm, Qn.
             out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
                                         "%s.f32 q%d, q%d, q%d", op, Vd, Vn, Vm);
           } else {
             Unknown(instr);
           }
           break;
@@ skipping 160 matching lines @@
         }
         case 0xa: {
           // vpmin/vpmax.u<size> Dd, Dm, Dn.
           const char* op = instr->Bit(4) == 1 ? "vpmin" : "vpmax";
           out_buffer_pos_ +=
               SNPrintF(out_buffer_ + out_buffer_pos_, "%s.u%d d%d, d%d, d%d",
                        op, size, Vd, Vn, Vm);
           break;
         }
         case 0xd: {
-          if (instr->Bit(21) == 0 && instr->Bit(6) == 1 && instr->Bit(4) == 1) {
-            // vmul.f32 Qd, Qn, Qm
+          if (instr->Bits(21, 20) == 0 && instr->Bit(6) == 1 &&
+              instr->Bit(4) == 1) {
+            // vmul.f32 Qd, Qm, Qn
             out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
                                         "vmul.f32 q%d, q%d, q%d", Vd, Vn, Vm);
+          } else if (instr->Bits(21, 20) == 0 && instr->Bit(6) == 0 &&
+                     instr->Bit(4) == 0) {
+            // vpadd.f32 Dd, Dm, Dn.
+            out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
+                                        "vpadd.f32 d%d, d%d, d%d", Vd, Vn, Vm);
           } else {
             Unknown(instr);
           }
           break;
         }
         case 0xe: {
           if (instr->Bit(20) == 0 && instr->Bit(4) == 0) {
             const char* op = (instr->Bit(21) == 0) ? "vcge" : "vcgt";
             // vcge/vcgt.f32 Qd, Qm, Qn.
             out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
@@ skipping 494 matching lines @@
     pc += d.InstructionDecode(buffer, pc);
     v8::internal::PrintF(f, "%p    %08x      %s\n", static_cast<void*>(prev_pc),
                          *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
   }
 }
 
 
 }  // namespace disasm
 
 #endif  // V8_TARGET_ARCH_ARM