[WASM SIMD] Implement horizontal add for float and integer types.

src/wasm/wasm-opcodes.h

 // Copyright 2015 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef V8_WASM_OPCODES_H_
 #define V8_WASM_OPCODES_H_
 
 #include "src/globals.h"
 #include "src/machine-type.h"
 #include "src/runtime/runtime.h"
@@ skipping 272 matching lines @@
   V(I32AsmjsUConvertF64, 0xe3, i_d)
 
 #define FOREACH_SIMD_0_OPERAND_OPCODE(V) \
   V(F32x4Splat, 0xe500, s_f)             \
   V(F32x4Abs, 0xe503, s_s)               \
   V(F32x4Neg, 0xe504, s_s)               \
   V(F32x4Sqrt, 0xe505, s_s)              \
   V(F32x4RecipApprox, 0xe506, s_s)       \
   V(F32x4RecipSqrtApprox, 0xe507, s_s)   \
   V(F32x4Add, 0xe508, s_ss)              \
+  V(F32x4AddHoriz, 0xe5b9, s_ss)         \

[georgia.kouveli, 2017/04/20 14:53:06]

Perhaps pairwise add would be a better name than horizontal add? (I would think
horizontal add refers to adding up all the elements in a single vector).

[bbudge, 2017/04/21 20:18:58]

Intel and MIPS naming is horizontal, though they are really only pairwise like
ARM.

MIPS - hadd, hsub
Intel - PHADDS  (packed horizontal add)

It's challenging to design a portable operation for this, since the MIPS
operation widens the sum (to avoid overflow) and there is no FP variant. Intel
and ARM have the normal behavior here, which is to return the result modulo 2 ^
number of bits per lane. Intel has no type for byte-sized lanes, and it seems
less useful than the others, so I'm removing that operation from this CL.

   V(F32x4Sub, 0xe509, s_ss)              \
   V(F32x4Mul, 0xe50a, s_ss)              \
   V(F32x4Div, 0xe50b, s_ss)              \
   V(F32x4Min, 0xe50c, s_ss)              \
   V(F32x4Max, 0xe50d, s_ss)              \
   V(F32x4MinNum, 0xe50e, s_ss)           \
   V(F32x4MaxNum, 0xe50f, s_ss)           \
   V(F32x4RecipRefine, 0xe592, s_ss)      \
   V(F32x4RecipSqrtRefine, 0xe593, s_ss)  \
   V(F32x4Eq, 0xe510, s1x4_ss)            \
   V(F32x4Ne, 0xe511, s1x4_ss)            \
   V(F32x4Lt, 0xe512, s1x4_ss)            \
   V(F32x4Le, 0xe513, s1x4_ss)            \
   V(F32x4Gt, 0xe514, s1x4_ss)            \
   V(F32x4Ge, 0xe515, s1x4_ss)            \
   V(F32x4SConvertI32x4, 0xe519, s_s)     \
   V(F32x4UConvertI32x4, 0xe51a, s_s)     \
   V(I32x4Splat, 0xe51b, s_i)             \
   V(I32x4Neg, 0xe51e, s_s)               \
   V(I32x4Add, 0xe51f, s_ss)              \
+  V(I32x4AddHoriz, 0xe5ba, s_ss)         \
   V(I32x4Sub, 0xe520, s_ss)              \
   V(I32x4Mul, 0xe521, s_ss)              \
   V(I32x4MinS, 0xe522, s_ss)             \
   V(I32x4MaxS, 0xe523, s_ss)             \
   V(I32x4Eq, 0xe526, s1x4_ss)            \
   V(I32x4Ne, 0xe527, s1x4_ss)            \
   V(I32x4LtS, 0xe528, s1x4_ss)           \
   V(I32x4LeS, 0xe529, s1x4_ss)           \
   V(I32x4GtS, 0xe52a, s1x4_ss)           \
   V(I32x4GeS, 0xe52b, s1x4_ss)           \
   V(I32x4SConvertF32x4, 0xe52f, s_s)     \
   V(I32x4UConvertF32x4, 0xe537, s_s)     \
   V(I32x4SConvertI16x8Low, 0xe594, s_s)  \
   V(I32x4SConvertI16x8High, 0xe595, s_s) \
   V(I32x4UConvertI16x8Low, 0xe596, s_s)  \
   V(I32x4UConvertI16x8High, 0xe597, s_s) \
   V(I32x4MinU, 0xe530, s_ss)             \
   V(I32x4MaxU, 0xe531, s_ss)             \
   V(I32x4LtU, 0xe533, s1x4_ss)           \
   V(I32x4LeU, 0xe534, s1x4_ss)           \
   V(I32x4GtU, 0xe535, s1x4_ss)           \
   V(I32x4GeU, 0xe536, s1x4_ss)           \
   V(I16x8Splat, 0xe538, s_i)             \
   V(I16x8Neg, 0xe53b, s_s)               \
   V(I16x8Add, 0xe53c, s_ss)              \
   V(I16x8AddSaturateS, 0xe53d, s_ss)     \
+  V(I16x8AddHoriz, 0xe5bb, s_ss)         \
   V(I16x8Sub, 0xe53e, s_ss)              \
   V(I16x8SubSaturateS, 0xe53f, s_ss)     \
   V(I16x8Mul, 0xe540, s_ss)              \
   V(I16x8MinS, 0xe541, s_ss)             \
   V(I16x8MaxS, 0xe542, s_ss)             \
   V(I16x8Eq, 0xe545, s1x8_ss)            \
   V(I16x8Ne, 0xe546, s1x8_ss)            \
   V(I16x8LtS, 0xe547, s1x8_ss)           \
   V(I16x8LeS, 0xe548, s1x8_ss)           \
   V(I16x8GtS, 0xe549, s1x8_ss)           \
   V(I16x8GeS, 0xe54a, s1x8_ss)           \
   V(I16x8AddSaturateU, 0xe54e, s_ss)     \
   V(I16x8SubSaturateU, 0xe54f, s_ss)     \
   V(I16x8MinU, 0xe550, s_ss)             \
   V(I16x8MaxU, 0xe551, s_ss)             \
   V(I16x8LtU, 0xe553, s1x8_ss)           \
   V(I16x8LeU, 0xe554, s1x8_ss)           \
   V(I16x8GtU, 0xe555, s1x8_ss)           \
   V(I16x8GeU, 0xe556, s1x8_ss)           \
   V(I16x8SConvertI32x4, 0xe598, s_ss)    \
   V(I16x8UConvertI32x4, 0xe599, s_ss)    \
   V(I16x8SConvertI8x16Low, 0xe59a, s_s)  \
   V(I16x8SConvertI8x16High, 0xe59b, s_s) \
   V(I16x8UConvertI8x16Low, 0xe59c, s_s)  \
   V(I16x8UConvertI8x16High, 0xe59d, s_s) \
   V(I8x16Splat, 0xe557, s_i)             \
   V(I8x16Neg, 0xe55a, s_s)               \
   V(I8x16Add, 0xe55b, s_ss)              \
   V(I8x16AddSaturateS, 0xe55c, s_ss)     \
+  V(I8x16AddHoriz, 0xe5bc, s_ss)         \
   V(I8x16Sub, 0xe55d, s_ss)              \
   V(I8x16SubSaturateS, 0xe55e, s_ss)     \
   V(I8x16Mul, 0xe55f, s_ss)              \
   V(I8x16MinS, 0xe560, s_ss)             \
   V(I8x16MaxS, 0xe561, s_ss)             \
   V(I8x16Eq, 0xe564, s1x16_ss)           \
   V(I8x16Ne, 0xe565, s1x16_ss)           \
   V(I8x16LtS, 0xe566, s1x16_ss)          \
   V(I8x16LeS, 0xe567, s1x16_ss)          \
   V(I8x16GtS, 0xe568, s1x16_ss)          \
@@ skipping 397 matching lines @@
       default:
         return "<unknown>";
     }
   }
 };
 }  // namespace wasm
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_WASM_OPCODES_H_