[WASM SIMD] Implement horizontal add for float and integer types.

src/arm/simulator-arm.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <stdarg.h>
 #include <stdlib.h>
 #include <cmath>
 
 #if V8_TARGET_ARCH_ARM
 
@@ skipping 4255 matching lines @@
   T dst[kElems], src1[kElems], src2[kElems];
   simulator->get_neon_register<T, kDoubleSize>(Vn, src1);
   simulator->get_neon_register<T, kDoubleSize>(Vm, src2);
   for (int i = 0; i < kPairs; i++) {
     dst[i] = MinMax(src1[i * 2], src1[i * 2 + 1], min);
     dst[i + kPairs] = MinMax(src2[i * 2], src2[i * 2 + 1], min);
   }
   simulator->set_neon_register<T, kDoubleSize>(Vd, dst);
 }
 
+template <typename T>
+void PairwiseAdd(Simulator* simulator, int Vd, int Vm, int Vn) {
+  static const int kElems = kDoubleSize / sizeof(T);
+  static const int kPairs = kElems / 2;
+  T dst[kElems], src1[kElems], src2[kElems];
+  simulator->get_neon_register<T, kDoubleSize>(Vn, src1);
+  simulator->get_neon_register<T, kDoubleSize>(Vm, src2);
+  for (int i = 0; i < kPairs; i++) {
+    dst[i] = src1[i * 2] + src1[i * 2 + 1];
+    dst[i + kPairs] = src2[i * 2] + src2[i * 2 + 1];
+  }
+  simulator->set_neon_register<T, kDoubleSize>(Vd, dst);
+}
+
 void Simulator::DecodeSpecialCondition(Instruction* instr) {
   switch (instr->SpecialValue()) {
     case 4: {
       int Vd, Vm, Vn;
       if (instr->Bit(6) == 0) {
         Vd = instr->VFPDRegValue(kDoublePrecision);
         Vm = instr->VFPMRegValue(kDoublePrecision);
         Vn = instr->VFPNRegValue(kDoublePrecision);
       } else {
         Vd = instr->VFPDRegValue(kSimd128Precision);
@@ skipping 191 matching lines @@
               break;
             case Neon32:
               PairwiseMinMax<int32_t>(this, Vd, Vm, Vn, min);
               break;
             default:
               UNREACHABLE();
               break;
           }
           break;
         }
+        case 0xb: {
+          // vpadd.i<size> Dd, Dm, Dn.
+          NeonSize size = static_cast<NeonSize>(instr->Bits(21, 20));
+          switch (size) {
+            case Neon8:
+              PairwiseAdd<int8_t>(this, Vd, Vm, Vn);
+              break;
+            case Neon16:
+              PairwiseAdd<int16_t>(this, Vd, Vm, Vn);
+              break;
+            case Neon32:
+              PairwiseAdd<int32_t>(this, Vd, Vm, Vn);
+              break;
+            default:
+              UNREACHABLE();
+              break;
+          }
+          break;
+        }
         case 0xd: {
           if (instr->Bit(4) == 0) {
             float src1[4], src2[4];
             get_neon_register(Vn, src1);
             get_neon_register(Vm, src2);
             for (int i = 0; i < 4; i++) {
               if (instr->Bit(21) == 0) {
                 // vadd.f32 Qd, Qm, Qn.
                 src1[i] = src1[i] + src2[i];
               } else {
@@ skipping 328 matching lines @@
             case Neon32:
               PairwiseMinMax<uint32_t>(this, Vd, Vm, Vn, min);
               break;
             default:
               UNREACHABLE();
               break;
           }
           break;
         }
         case 0xd: {
-          if (instr->Bit(21) == 0 && instr->Bit(6) == 1 && instr->Bit(4) == 1) {
+          if (instr->Bits(21, 20) == 0 && instr->Bit(6) == 1 &&
+              instr->Bit(4) == 1) {
             // vmul.f32 Qd, Qn, Qm
             float src1[4], src2[4];
             get_neon_register(Vn, src1);
             get_neon_register(Vm, src2);
             for (int i = 0; i < 4; i++) {
               src1[i] = src1[i] * src2[i];
             }
             set_neon_register(Vd, src1);
+          } else if (instr->Bits(21, 20) == 0 && instr->Bit(6) == 0 &&
+                     instr->Bit(4) == 0) {
+            // vpadd.f32 Dd, Dn, Dm
+            PairwiseAdd<float>(this, Vd, Vm, Vn);
           } else {
             UNIMPLEMENTED();
           }
           break;
         }
         case 0xe: {
           if (instr->Bit(20) == 0 && instr->Bit(4) == 0) {
             // vcge/vcgt.f32 Qd, Qm, Qn
             bool ge = instr->Bit(21) == 0;
             float src1[4], src2[4];
@@ skipping 1190 matching lines @@
   processor->prev_ = nullptr;
   processor->next_ = nullptr;
 }
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // USE_SIMULATOR
 
 #endif  // V8_TARGET_ARCH_ARM