[WASM SIMD] Implement primitive shuffles.

src/compiler/arm/instruction-selector-arm.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/base/adapters.h"
 #include "src/base/bits.h"
 #include "src/compiler/instruction-selector-impl.h"
 #include "src/compiler/node-matchers.h"
 #include "src/compiler/node-properties.h"
 
@@ skipping 73 matching lines @@
                  g.UseRegister(node->InputAt(0)));
 }
 
 void VisitRRR(InstructionSelector* selector, ArchOpcode opcode, Node* node) {
   ArmOperandGenerator g(selector);
   selector->Emit(opcode, g.DefineAsRegister(node),
                  g.UseRegister(node->InputAt(0)),
                  g.UseRegister(node->InputAt(1)));
 }
 
+void VisitRRRShuffle(InstructionSelector* selector, ArchOpcode opcode,
+                     Node* node) {
+  ArmOperandGenerator g(selector);
+  // Swap inputs to save an instruction in the CodeGenerator for High ops.
+  if (opcode == kArmS32x4ZipRight || opcode == kArmS32x4UnzipRight ||
+      opcode == kArmS32x4TransposeRight || opcode == kArmS16x8ZipRight ||
+      opcode == kArmS16x8UnzipRight || opcode == kArmS16x8TransposeRight ||
+      opcode == kArmS8x16ZipRight || opcode == kArmS8x16UnzipRight ||
+      opcode == kArmS8x16TransposeRight) {
+    Node* in0 = node->InputAt(0);
+    Node* in1 = node->InputAt(1);
+    node->ReplaceInput(0, in1);
+    node->ReplaceInput(1, in0);
+  }
+  // Use DefineSameAsFirst for binary ops that clobber their inputs, e.g. the
+  // NEON vzip, vuzp, and vtrn instructions.
+  selector->Emit(opcode, g.DefineSameAsFirst(node),
+                 g.UseRegister(node->InputAt(0)),
+                 g.UseRegister(node->InputAt(1)));
+}
+
 void VisitRRRR(InstructionSelector* selector, ArchOpcode opcode, Node* node) {
   ArmOperandGenerator g(selector);
   // Use DefineSameAsFirst for ternary ops that clobber their first input,
   // e.g. the NEON vbsl instruction.
   selector->Emit(
       opcode, g.DefineSameAsFirst(node), g.UseRegister(node->InputAt(0)),
       g.UseRegister(node->InputAt(1)), g.UseRegister(node->InputAt(2)));
 }
 
 void VisitRRI(InstructionSelector* selector, ArchOpcode opcode, Node* node) {
@@ skipping 2222 matching lines @@
   V(F32x4Abs, kArmF32x4Abs)                         \
   V(F32x4Neg, kArmF32x4Neg)                         \
   V(F32x4RecipApprox, kArmF32x4RecipApprox)         \
   V(F32x4RecipSqrtApprox, kArmF32x4RecipSqrtApprox) \
   V(I32x4SConvertF32x4, kArmI32x4SConvertF32x4)     \
   V(I32x4Neg, kArmI32x4Neg)                         \
   V(I32x4UConvertF32x4, kArmI32x4UConvertF32x4)     \
   V(I16x8Neg, kArmI16x8Neg)                         \
   V(I8x16Neg, kArmI8x16Neg)                         \
   V(S128Not, kArmS128Not)                           \
+  V(S64x2Reverse, kArmS64x2Reverse)                 \
+  V(S32x2Reverse, kArmS32x2Reverse)                 \
+  V(S16x4Reverse, kArmS16x4Reverse)                 \
+  V(S16x2Reverse, kArmS16x2Reverse)                 \
+  V(S8x8Reverse, kArmS8x8Reverse)                   \
+  V(S8x4Reverse, kArmS8x4Reverse)                   \
+  V(S8x2Reverse, kArmS8x2Reverse)                   \
   V(S1x4Not, kArmS128Not)                           \
   V(S1x4AnyTrue, kArmS1x4AnyTrue)                   \
   V(S1x4AllTrue, kArmS1x4AllTrue)                   \
   V(S1x8Not, kArmS128Not)                           \
   V(S1x8AnyTrue, kArmS1x8AnyTrue)                   \
   V(S1x8AllTrue, kArmS1x8AllTrue)                   \
   V(S1x16Not, kArmS128Not)                          \
   V(S1x16AnyTrue, kArmS1x16AnyTrue)                 \
   V(S1x16AllTrue, kArmS1x16AllTrue)
 
@@ skipping 73 matching lines @@
   V(S1x4And, kArmS128And)                           \
   V(S1x4Or, kArmS128Or)                             \
   V(S1x4Xor, kArmS128Xor)                           \
   V(S1x8And, kArmS128And)                           \
   V(S1x8Or, kArmS128Or)                             \
   V(S1x8Xor, kArmS128Xor)                           \
   V(S1x16And, kArmS128And)                          \
   V(S1x16Or, kArmS128Or)                            \
   V(S1x16Xor, kArmS128Xor)
 
+#define SIMD_SHUFFLE_OP_LIST(V) \
+  V(S32x4ZipLeft)               \
+  V(S32x4ZipRight)              \
+  V(S32x4UnzipLeft)             \
+  V(S32x4UnzipRight)            \
+  V(S32x4TransposeLeft)         \
+  V(S32x4TransposeRight)        \
+  V(S16x8ZipLeft)               \
+  V(S16x8ZipRight)              \
+  V(S16x8UnzipLeft)             \
+  V(S16x8UnzipRight)            \
+  V(S16x8TransposeLeft)         \
+  V(S16x8TransposeRight)        \
+  V(S8x16ZipLeft)               \
+  V(S8x16ZipRight)              \
+  V(S8x16UnzipLeft)             \
+  V(S8x16UnzipRight)            \
+  V(S8x16TransposeLeft)         \
+  V(S8x16TransposeRight)
+
 #define SIMD_VISIT_SPLAT(Type)                               \
   void InstructionSelector::Visit##Type##Splat(Node* node) { \
     VisitRR(this, kArm##Type##Splat, node);                  \
   }
 SIMD_TYPE_LIST(SIMD_VISIT_SPLAT)
 #undef SIMD_VISIT_SPLAT
 
 #define SIMD_VISIT_EXTRACT_LANE(Type)                              \
   void InstructionSelector::Visit##Type##ExtractLane(Node* node) { \
     VisitRRI(this, kArm##Type##ExtractLane, node);                 \
@@ skipping 37 matching lines @@
 SIMD_BINOP_LIST(SIMD_VISIT_BINOP)
 #undef SIMD_VISIT_BINOP
 
 #define SIMD_VISIT_SELECT_OP(format)                             \
   void InstructionSelector::VisitS##format##Select(Node* node) { \
     VisitRRRR(this, kArmS128Select, node);                       \
   }
 SIMD_FORMAT_LIST(SIMD_VISIT_SELECT_OP)
 #undef SIMD_VISIT_SELECT_OP
 
+#define SIMD_VISIT_SHUFFLE_OP(Name)                   \
+  void InstructionSelector::Visit##Name(Node* node) { \
+    VisitRRRShuffle(this, kArm##Name, node);          \
+  }
+SIMD_SHUFFLE_OP_LIST(SIMD_VISIT_SHUFFLE_OP)
+#undef SIMD_VISIT_SHUFFLE_OP
+
+void InstructionSelector::VisitS8x16Concat(Node* node) {
+  ArmOperandGenerator g(this);
+  int32_t imm = OpParameter<int32_t>(node);
+  Emit(kArmS8x16Concat, g.DefineAsRegister(node),
+       g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)),
+       g.UseImmediate(imm));
+}
+
 void InstructionSelector::VisitInt32AbsWithOverflow(Node* node) {
   UNREACHABLE();
 }
 
 void InstructionSelector::VisitInt64AbsWithOverflow(Node* node) {
   UNREACHABLE();
 }
 
 // static
 MachineOperatorBuilder::Flags
@@ skipping 28 matching lines @@
   Vector<MachineType> req_aligned = Vector<MachineType>::New(2);
   req_aligned[0] = MachineType::Float32();
   req_aligned[1] = MachineType::Float64();
   return MachineOperatorBuilder::AlignmentRequirements::
       SomeUnalignedAccessUnsupported(req_aligned, req_aligned);
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8