[WASM SIMD] Implement primitive shuffles.

src/compiler/arm/code-generator-arm.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/compiler/code-generator.h"
 
 #include "src/arm/macro-assembler-arm.h"
 #include "src/assembler-inl.h"
 #include "src/compilation-info.h"
 #include "src/compiler/code-generator-impl.h"
@@ skipping 2010 matching lines @@
       __ vmvn(i.OutputSimd128Register(), i.InputSimd128Register(0));
       break;
     }
     case kArmS128Select: {
       // vbsl clobbers the mask input so make sure it was DefineSameAsFirst.
       DCHECK(i.OutputSimd128Register().is(i.InputSimd128Register(0)));
       __ vbsl(i.OutputSimd128Register(), i.InputSimd128Register(1),
               i.InputSimd128Register(2));
       break;
     }
+    case kArmS32x4ZipLeft: {

[martyn.capewell, 2017/04/10 16:46:55]

It might be helpful to add a comment to each of these, expressing the
transformation. For example, this is 3210 -> 1100, assuming lowest index lane on
the right. Though maybe your naming implies that lowest index is on the left.

[bbudge, 2017/04/10 23:26:47]

Here's what this is supposed to do:
src0 = 0,1,2,3 (from low to high)
src1 = 4,5,6,7
After the vmov
dst (src0) = 0,1,4,5
After vzip
0,4,1,5

I'll add some comments.

+      Simd128Register dst = i.OutputSimd128Register(),
+                      src1 = i.InputSimd128Register(1);
+      DCHECK(dst.is(i.InputSimd128Register(0)));
+      __ vmov(dst.high(), src1.low());

[martyn.capewell, 2017/04/10 16:46:55]

If the assembler supports it, you could use:
  vdup.32 dst.high, src.low[1]
  vdup.32 dst.low, src.low[0]

This removes the constraint on dst == src, as do the rest below.

+      __ vzip(Neon32, dst.low(), dst.high());
+      break;
+    }
+    case kArmS32x4ZipRight: {

[martyn.capewell, 2017/04/10 16:46:55]

  vdup.32 dst.low, src.high[0]
  vdup.32 dst.high, src.high[1]

+      Simd128Register dst = i.OutputSimd128Register(),
+                      src1 = i.InputSimd128Register(1);
+      DCHECK(dst.is(i.InputSimd128Register(0)));
+      __ vmov(dst.low(), src1.high());
+      __ vzip(Neon32, dst.low(), dst.high());
+      break;
+    }
+    case kArmS32x4UnzipLeft: {

[martyn.capewell, 2017/04/10 16:46:55]

  vmovn.i64 dst.low, src
  vmov dst.high, dst.low

+      Simd128Register dst = i.OutputSimd128Register(),
+                      src1 = i.InputSimd128Register(1);
+      DCHECK(dst.is(i.InputSimd128Register(0)));
+      __ vmov(kScratchQuadReg, src1);
+      __ vuzp(Neon32, dst, kScratchQuadReg);
+      __ veor(kDoubleRegZero, kDoubleRegZero, kDoubleRegZero);
+      break;
+    }
+    case kArmS32x4UnzipRight: {

[martyn.capewell, 2017/04/10 16:46:55]

  vshrn.i64 dst.low, src, #32
  vmov dst.high, dst.low

+      Simd128Register dst = i.OutputSimd128Register(),
+                      src1 = i.InputSimd128Register(1);
+      DCHECK(dst.is(i.InputSimd128Register(0)));
+      __ vmov(kScratchQuadReg, src1);
+      __ vuzp(Neon32, kScratchQuadReg, dst);
+      __ veor(kDoubleRegZero, kDoubleRegZero, kDoubleRegZero);
+      break;
+    }
+    case kArmS32x4TransposeLeft: {

[martyn.capewell, 2017/04/10 16:46:55]

  vdup.32 dst.low, src.low[0]
  vdup.32 dst.high, src.high[0]

+      Simd128Register dst = i.OutputSimd128Register(),
+                      src1 = i.InputSimd128Register(1);
+      DCHECK(dst.is(i.InputSimd128Register(0)));
+      __ vmov(kScratchQuadReg, src1);
+      __ vtrn(Neon32, dst, kScratchQuadReg);
+      __ veor(kDoubleRegZero, kDoubleRegZero, kDoubleRegZero);
+      break;
+    }
+    case kArmS32x4TransposeRight: {

[martyn.capewell, 2017/04/10 16:46:56]

  vdup dst.low, src.low[1]
  vdup dst.high, src.high[1]

+      Simd128Register dst = i.OutputSimd128Register(),
+                      src1 = i.InputSimd128Register(1);
+      DCHECK(dst.is(i.InputSimd128Register(0)));
+      __ vmov(kScratchQuadReg, src1);
+      __ vtrn(Neon32, kScratchQuadReg, dst);
+      __ veor(kDoubleRegZero, kDoubleRegZero, kDoubleRegZero);
+      break;
+    }
+    case kArmS16x8ZipLeft: {
+      Simd128Register dst = i.OutputSimd128Register(),
+                      src1 = i.InputSimd128Register(1);
+      DCHECK(dst.is(i.InputSimd128Register(0)));
+      __ vmov(dst.high(), src1.low());
+      __ vzip(Neon16, dst.low(), dst.high());
+      break;
+    }
+    case kArmS16x8ZipRight: {
+      Simd128Register dst = i.OutputSimd128Register(),
+                      src1 = i.InputSimd128Register(1);
+      DCHECK(dst.is(i.InputSimd128Register(0)));
+      __ vmov(dst.low(), src1.high());
+      __ vzip(Neon16, dst.low(), dst.high());
+      break;
+    }
+    case kArmS16x8UnzipLeft: {

[martyn.capewell, 2017/04/10 16:46:55]

  vmovn.i32 dst.low, src
  vmov dst.high, dst.low

+      Simd128Register dst = i.OutputSimd128Register(),
+                      src1 = i.InputSimd128Register(1);
+      DCHECK(dst.is(i.InputSimd128Register(0)));
+      __ vmov(kScratchQuadReg, src1);
+      __ vuzp(Neon16, dst, kScratchQuadReg);
+      __ veor(kDoubleRegZero, kDoubleRegZero, kDoubleRegZero);
+      break;
+    }
+    case kArmS16x8UnzipRight: {

[martyn.capewell, 2017/04/10 16:46:55]

  vshrn.i32 dst.low, src, #16
  vmov dst.high, dst.low

+      Simd128Register dst = i.OutputSimd128Register(),
+                      src1 = i.InputSimd128Register(1);
+      DCHECK(dst.is(i.InputSimd128Register(0)));
+      __ vmov(kScratchQuadReg, src1);
+      __ vuzp(Neon16, kScratchQuadReg, dst);
+      __ veor(kDoubleRegZero, kDoubleRegZero, kDoubleRegZero);
+      break;
+    }
+    case kArmS16x8TransposeLeft: {
+      Simd128Register dst = i.OutputSimd128Register(),
+                      src1 = i.InputSimd128Register(1);
+      DCHECK(dst.is(i.InputSimd128Register(0)));
+      __ vmov(kScratchQuadReg, src1);
+      __ vtrn(Neon16, dst, kScratchQuadReg);
+      __ veor(kDoubleRegZero, kDoubleRegZero, kDoubleRegZero);
+      break;
+    }
+    case kArmS16x8TransposeRight: {
+      Simd128Register dst = i.OutputSimd128Register(),
+                      src1 = i.InputSimd128Register(1);
+      DCHECK(dst.is(i.InputSimd128Register(0)));
+      __ vmov(kScratchQuadReg, src1);
+      __ vtrn(Neon16, kScratchQuadReg, dst);
+      __ veor(kDoubleRegZero, kDoubleRegZero, kDoubleRegZero);
+      break;
+    }
+    case kArmS8x16ZipLeft: {
+      Simd128Register dst = i.OutputSimd128Register(),
+                      src1 = i.InputSimd128Register(1);
+      DCHECK(dst.is(i.InputSimd128Register(0)));
+      __ vmov(dst.high(), src1.low());
+      __ vzip(Neon8, dst.low(), dst.high());
+      break;
+    }
+    case kArmS8x16ZipRight: {
+      Simd128Register dst = i.OutputSimd128Register(),
+                      src1 = i.InputSimd128Register(1);
+      DCHECK(dst.is(i.InputSimd128Register(0)));
+      __ vmov(dst.low(), src1.high());
+      __ vzip(Neon8, dst.low(), dst.high());
+      break;
+    }
+    case kArmS8x16UnzipLeft: {

[martyn.capewell, 2017/04/10 16:46:55]

  vmovn.i16 dst.low, src
  vmov dst.high, dst.low

+      Simd128Register dst = i.OutputSimd128Register(),
+                      src1 = i.InputSimd128Register(1);
+      DCHECK(dst.is(i.InputSimd128Register(0)));
+      __ vmov(kScratchQuadReg, src1);
+      __ vuzp(Neon8, dst, kScratchQuadReg);
+      __ veor(kDoubleRegZero, kDoubleRegZero, kDoubleRegZero);
+      break;
+    }
+    case kArmS8x16UnzipRight: {

[martyn.capewell, 2017/04/10 16:46:55]

  vshrn.i16, dst.low, src, #8
  vmov dst.high, dst.low

+      Simd128Register dst = i.OutputSimd128Register(),
+                      src1 = i.InputSimd128Register(1);
+      DCHECK(dst.is(i.InputSimd128Register(0)));
+      __ vmov(kScratchQuadReg, src1);
+      __ vuzp(Neon8, kScratchQuadReg, dst);
+      __ veor(kDoubleRegZero, kDoubleRegZero, kDoubleRegZero);
+      break;
+    }
+    case kArmS8x16TransposeLeft: {
+      Simd128Register dst = i.OutputSimd128Register(),
+                      src1 = i.InputSimd128Register(1);
+      DCHECK(dst.is(i.InputSimd128Register(0)));
+      __ vmov(kScratchQuadReg, src1);
+      __ vtrn(Neon8, dst, kScratchQuadReg);
+      __ veor(kDoubleRegZero, kDoubleRegZero, kDoubleRegZero);
+      break;
+    }
+    case kArmS8x16TransposeRight: {
+      Simd128Register dst = i.OutputSimd128Register(),
+                      src1 = i.InputSimd128Register(1);
+      DCHECK(dst.is(i.InputSimd128Register(0)));
+      __ vmov(kScratchQuadReg, src1);
+      __ vtrn(Neon8, kScratchQuadReg, dst);
+      __ veor(kDoubleRegZero, kDoubleRegZero, kDoubleRegZero);
+      break;
+    }
+    case kArmS8x16Concat: {
+      __ vext(i.OutputSimd128Register(), i.InputSimd128Register(0),
+              i.InputSimd128Register(1), i.InputInt4(2));
+      break;
+    }
+    case kArmS64x2Reverse: {

[martyn.capewell, 2017/04/10 16:46:55]

vext(dst, src, src, 8);

[bbudge, 2017/04/10 23:26:47]

Nice. However, since we expose VEXT (as S8x16Concat) this instruction would be
redundant, so I'm removing S64x2Reverse from the prototype.

+      Simd128Register dst = i.OutputSimd128Register(),
+                      src = i.InputSimd128Register(0);
+      if (!dst.is(src)) __ vmov(dst, src);
+      __ vswp(dst.low(), dst.high());
+      break;
+    }
+    case kArmS32x2Reverse: {
+      __ vrev64(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0));
+      break;
+    }
+    case kArmS16x4Reverse: {
+      __ vrev64(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0));
+      break;
+    }
+    case kArmS16x2Reverse: {
+      __ vrev32(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0));
+      break;
+    }
+    case kArmS8x8Reverse: {
+      __ vrev64(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0));
+      break;
+    }
+    case kArmS8x4Reverse: {
+      __ vrev32(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0));
+      break;
+    }
+    case kArmS8x2Reverse: {
+      __ vrev16(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0));
+      break;
+    }
     case kArmS1x4AnyTrue: {
       const QwNeonRegister& src = i.InputSimd128Register(0);
       __ vpmax(NeonU32, kScratchDoubleReg, src.low(), src.high());
       __ vpmax(NeonU32, kScratchDoubleReg, kScratchDoubleReg,
                kScratchDoubleReg);
       __ ExtractLane(i.OutputRegister(), kScratchDoubleReg, NeonS32, 0);
       break;
     }
     case kArmS1x4AllTrue: {
       const QwNeonRegister& src = i.InputSimd128Register(0);
@@ skipping 790 matching lines @@
       padding_size -= v8::internal::Assembler::kInstrSize;
     }
   }
 }
 
 #undef __
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8