[WASM SIMD] Implement packing and unpacking integer conversions.

src/compiler/instruction-selector.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/compiler/instruction-selector.h"
 
 #include <limits>
 
 #include "src/assembler-inl.h"
 #include "src/base/adapters.h"
@@ skipping 1510 matching lines @@
     case IrOpcode::kF32x4Le:
       return MarkAsSimd1x4(node), VisitF32x4Le(node);
     case IrOpcode::kI32x4Splat:
       return MarkAsSimd128(node), VisitI32x4Splat(node);
     case IrOpcode::kI32x4ExtractLane:
       return MarkAsWord32(node), VisitI32x4ExtractLane(node);
     case IrOpcode::kI32x4ReplaceLane:
       return MarkAsSimd128(node), VisitI32x4ReplaceLane(node);
     case IrOpcode::kI32x4SConvertF32x4:
       return MarkAsSimd128(node), VisitI32x4SConvertF32x4(node);
+    case IrOpcode::kI32x4SConvertI16x8Low:
+      return MarkAsSimd128(node), VisitI32x4SConvertI16x8Low(node);
+    case IrOpcode::kI32x4SConvertI16x8High:
+      return MarkAsSimd128(node), VisitI32x4SConvertI16x8High(node);
     case IrOpcode::kI32x4Neg:
       return MarkAsSimd128(node), VisitI32x4Neg(node);
     case IrOpcode::kI32x4Shl:
       return MarkAsSimd128(node), VisitI32x4Shl(node);
     case IrOpcode::kI32x4ShrS:
       return MarkAsSimd128(node), VisitI32x4ShrS(node);
     case IrOpcode::kI32x4Add:
       return MarkAsSimd128(node), VisitI32x4Add(node);
     case IrOpcode::kI32x4Sub:
       return MarkAsSimd128(node), VisitI32x4Sub(node);
     case IrOpcode::kI32x4Mul:
       return MarkAsSimd128(node), VisitI32x4Mul(node);
     case IrOpcode::kI32x4MinS:
       return MarkAsSimd128(node), VisitI32x4MinS(node);
     case IrOpcode::kI32x4MaxS:
       return MarkAsSimd128(node), VisitI32x4MaxS(node);
     case IrOpcode::kI32x4Eq:
       return MarkAsSimd1x4(node), VisitI32x4Eq(node);
     case IrOpcode::kI32x4Ne:
       return MarkAsSimd1x4(node), VisitI32x4Ne(node);
     case IrOpcode::kI32x4LtS:
       return MarkAsSimd1x4(node), VisitI32x4LtS(node);
     case IrOpcode::kI32x4LeS:
       return MarkAsSimd1x4(node), VisitI32x4LeS(node);
     case IrOpcode::kI32x4UConvertF32x4:
       return MarkAsSimd128(node), VisitI32x4UConvertF32x4(node);
+    case IrOpcode::kI32x4UConvertI16x8Low:
+      return MarkAsSimd128(node), VisitI32x4UConvertI16x8Low(node);
+    case IrOpcode::kI32x4UConvertI16x8High:
+      return MarkAsSimd128(node), VisitI32x4UConvertI16x8High(node);
     case IrOpcode::kI32x4ShrU:
       return MarkAsSimd128(node), VisitI32x4ShrU(node);
     case IrOpcode::kI32x4MinU:
       return MarkAsSimd128(node), VisitI32x4MinU(node);
     case IrOpcode::kI32x4MaxU:
       return MarkAsSimd128(node), VisitI32x4MaxU(node);
     case IrOpcode::kI32x4LtU:
       return MarkAsSimd1x4(node), VisitI32x4LtU(node);
     case IrOpcode::kI32x4LeU:
       return MarkAsSimd1x4(node), VisitI32x4LeU(node);
     case IrOpcode::kI16x8Splat:
       return MarkAsSimd128(node), VisitI16x8Splat(node);
     case IrOpcode::kI16x8ExtractLane:
       return MarkAsWord32(node), VisitI16x8ExtractLane(node);
     case IrOpcode::kI16x8ReplaceLane:
       return MarkAsSimd128(node), VisitI16x8ReplaceLane(node);
+    case IrOpcode::kI16x8SConvertI8x16Low:
+      return MarkAsSimd128(node), VisitI16x8SConvertI8x16Low(node);
+    case IrOpcode::kI16x8SConvertI8x16High:
+      return MarkAsSimd128(node), VisitI16x8SConvertI8x16High(node);
     case IrOpcode::kI16x8Neg:
       return MarkAsSimd128(node), VisitI16x8Neg(node);
     case IrOpcode::kI16x8Shl:
       return MarkAsSimd128(node), VisitI16x8Shl(node);
     case IrOpcode::kI16x8ShrS:
       return MarkAsSimd128(node), VisitI16x8ShrS(node);
+    case IrOpcode::kI16x8SConvertI32x4:
+      return MarkAsSimd128(node), VisitI16x8SConvertI32x4(node);
     case IrOpcode::kI16x8Add:
       return MarkAsSimd128(node), VisitI16x8Add(node);
     case IrOpcode::kI16x8AddSaturateS:
       return MarkAsSimd128(node), VisitI16x8AddSaturateS(node);
     case IrOpcode::kI16x8Sub:
       return MarkAsSimd128(node), VisitI16x8Sub(node);
     case IrOpcode::kI16x8SubSaturateS:
       return MarkAsSimd128(node), VisitI16x8SubSaturateS(node);
     case IrOpcode::kI16x8Mul:
       return MarkAsSimd128(node), VisitI16x8Mul(node);
     case IrOpcode::kI16x8MinS:
       return MarkAsSimd128(node), VisitI16x8MinS(node);
     case IrOpcode::kI16x8MaxS:
       return MarkAsSimd128(node), VisitI16x8MaxS(node);
     case IrOpcode::kI16x8Eq:
       return MarkAsSimd1x8(node), VisitI16x8Eq(node);
     case IrOpcode::kI16x8Ne:
       return MarkAsSimd1x8(node), VisitI16x8Ne(node);
     case IrOpcode::kI16x8LtS:
       return MarkAsSimd1x8(node), VisitI16x8LtS(node);
     case IrOpcode::kI16x8LeS:
       return MarkAsSimd1x8(node), VisitI16x8LeS(node);
+    case IrOpcode::kI16x8UConvertI8x16Low:
+      return MarkAsSimd128(node), VisitI16x8UConvertI8x16Low(node);
+    case IrOpcode::kI16x8UConvertI8x16High:
+      return MarkAsSimd128(node), VisitI16x8UConvertI8x16High(node);
     case IrOpcode::kI16x8ShrU:
       return MarkAsSimd128(node), VisitI16x8ShrU(node);
+    case IrOpcode::kI16x8UConvertI32x4:
+      return MarkAsSimd128(node), VisitI16x8UConvertI32x4(node);
     case IrOpcode::kI16x8AddSaturateU:
       return MarkAsSimd128(node), VisitI16x8AddSaturateU(node);
     case IrOpcode::kI16x8SubSaturateU:
       return MarkAsSimd128(node), VisitI16x8SubSaturateU(node);
     case IrOpcode::kI16x8MinU:
       return MarkAsSimd128(node), VisitI16x8MinU(node);
     case IrOpcode::kI16x8MaxU:
       return MarkAsSimd128(node), VisitI16x8MaxU(node);
     case IrOpcode::kI16x8LtU:
       return MarkAsSimd1x8(node), VisitI16x8LtU(node);
     case IrOpcode::kI16x8LeU:
       return MarkAsSimd1x8(node), VisitI16x8LeU(node);
     case IrOpcode::kI8x16Splat:
       return MarkAsSimd128(node), VisitI8x16Splat(node);
     case IrOpcode::kI8x16ExtractLane:
       return MarkAsWord32(node), VisitI8x16ExtractLane(node);
     case IrOpcode::kI8x16ReplaceLane:
       return MarkAsSimd128(node), VisitI8x16ReplaceLane(node);
     case IrOpcode::kI8x16Neg:
       return MarkAsSimd128(node), VisitI8x16Neg(node);
     case IrOpcode::kI8x16Shl:
       return MarkAsSimd128(node), VisitI8x16Shl(node);
     case IrOpcode::kI8x16ShrS:
       return MarkAsSimd128(node), VisitI8x16ShrS(node);
+    case IrOpcode::kI8x16SConvertI16x8:
+      return MarkAsSimd128(node), VisitI8x16SConvertI16x8(node);
     case IrOpcode::kI8x16Add:
       return MarkAsSimd128(node), VisitI8x16Add(node);
     case IrOpcode::kI8x16AddSaturateS:
       return MarkAsSimd128(node), VisitI8x16AddSaturateS(node);
     case IrOpcode::kI8x16Sub:
       return MarkAsSimd128(node), VisitI8x16Sub(node);
     case IrOpcode::kI8x16SubSaturateS:
       return MarkAsSimd128(node), VisitI8x16SubSaturateS(node);
     case IrOpcode::kI8x16Mul:
       return MarkAsSimd128(node), VisitI8x16Mul(node);
     case IrOpcode::kI8x16MinS:
       return MarkAsSimd128(node), VisitI8x16MinS(node);
     case IrOpcode::kI8x16MaxS:
       return MarkAsSimd128(node), VisitI8x16MaxS(node);
     case IrOpcode::kI8x16Eq:
       return MarkAsSimd1x16(node), VisitI8x16Eq(node);
     case IrOpcode::kI8x16Ne:
       return MarkAsSimd1x16(node), VisitI8x16Ne(node);
     case IrOpcode::kI8x16LtS:
       return MarkAsSimd1x16(node), VisitI8x16LtS(node);
     case IrOpcode::kI8x16LeS:
       return MarkAsSimd1x16(node), VisitI8x16LeS(node);
     case IrOpcode::kI8x16ShrU:
       return MarkAsSimd128(node), VisitI8x16ShrU(node);
+    case IrOpcode::kI8x16UConvertI16x8:
+      return MarkAsSimd128(node), VisitI8x16UConvertI16x8(node);
     case IrOpcode::kI8x16AddSaturateU:
       return MarkAsSimd128(node), VisitI8x16AddSaturateU(node);
     case IrOpcode::kI8x16SubSaturateU:
       return MarkAsSimd128(node), VisitI8x16SubSaturateU(node);
     case IrOpcode::kI8x16MinU:
       return MarkAsSimd128(node), VisitI8x16MinU(node);
     case IrOpcode::kI8x16MaxU:
       return MarkAsSimd128(node), VisitI8x16MaxU(node);
     case IrOpcode::kI8x16LtU:
       return MarkAsSimd1x16(node), VisitI8x16LtU(node);
@@ skipping 471 matching lines @@
 void InstructionSelector::VisitI32x4MaxU(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI32x4ShrU(Node* node) { UNIMPLEMENTED(); }
 #endif  // !V8_TARGET_ARCH_X64 && !V8_TARGET_ARCH_ARM
 
 #if !V8_TARGET_ARCH_ARM
 void InstructionSelector::VisitI32x4SConvertF32x4(Node* node) {
   UNIMPLEMENTED();
 }
 
+void InstructionSelector::VisitI32x4SConvertI16x8Low(Node* node) {
+  UNIMPLEMENTED();
+}
+
+void InstructionSelector::VisitI32x4SConvertI16x8High(Node* node) {
+  UNIMPLEMENTED();
+}
+
 void InstructionSelector::VisitI32x4Neg(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI32x4LtS(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI32x4LeS(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI32x4UConvertF32x4(Node* node) {
   UNIMPLEMENTED();
 }
 
+void InstructionSelector::VisitI32x4UConvertI16x8Low(Node* node) {
+  UNIMPLEMENTED();
+}
+
+void InstructionSelector::VisitI32x4UConvertI16x8High(Node* node) {
+  UNIMPLEMENTED();
+}
+
 void InstructionSelector::VisitI32x4LtU(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI32x4LeU(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI16x8Splat(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI16x8ExtractLane(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI16x8ReplaceLane(Node* node) { UNIMPLEMENTED(); }
 
+void InstructionSelector::VisitI16x8SConvertI8x16Low(Node* node) {
+  UNIMPLEMENTED();
+}
+
+void InstructionSelector::VisitI16x8SConvertI8x16High(Node* node) {
+  UNIMPLEMENTED();
+}
+
 void InstructionSelector::VisitI16x8Neg(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI16x8Shl(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI16x8ShrS(Node* node) { UNIMPLEMENTED(); }
 
+void InstructionSelector::VisitI16x8SConvertI32x4(Node* node) {
+  UNIMPLEMENTED();
+}
+
 void InstructionSelector::VisitI16x8Add(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI16x8AddSaturateS(Node* node) {
   UNIMPLEMENTED();
 }
 
 void InstructionSelector::VisitI16x8Sub(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI16x8SubSaturateS(Node* node) {
   UNIMPLEMENTED();
 }
 
 void InstructionSelector::VisitI16x8Mul(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI16x8MinS(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI16x8MaxS(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI16x8Eq(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI16x8Ne(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI16x8LtS(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI16x8LeS(Node* node) { UNIMPLEMENTED(); }
 
+void InstructionSelector::VisitI16x8UConvertI8x16Low(Node* node) {
+  UNIMPLEMENTED();
+}
+
+void InstructionSelector::VisitI16x8UConvertI8x16High(Node* node) {
+  UNIMPLEMENTED();
+}
+
 void InstructionSelector::VisitI16x8ShrU(Node* node) { UNIMPLEMENTED(); }
 
+void InstructionSelector::VisitI16x8UConvertI32x4(Node* node) {
+  UNIMPLEMENTED();
+}
+
 void InstructionSelector::VisitI16x8AddSaturateU(Node* node) {
   UNIMPLEMENTED();
 }
 
 void InstructionSelector::VisitI16x8SubSaturateU(Node* node) {
   UNIMPLEMENTED();
 }
 
 void InstructionSelector::VisitI16x8MinU(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI16x8MaxU(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI16x8LtU(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI16x8LeU(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI8x16Splat(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI8x16ExtractLane(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI8x16ReplaceLane(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI8x16Neg(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI8x16Shl(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI8x16ShrS(Node* node) { UNIMPLEMENTED(); }
 
+void InstructionSelector::VisitI8x16SConvertI16x8(Node* node) {
+  UNIMPLEMENTED();
+}
+
 void InstructionSelector::VisitI8x16Add(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI8x16AddSaturateS(Node* node) {
   UNIMPLEMENTED();
 }
 
 void InstructionSelector::VisitI8x16Sub(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI8x16SubSaturateS(Node* node) {
   UNIMPLEMENTED();
 }
 
 void InstructionSelector::VisitI8x16Mul(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI8x16MinS(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI8x16MaxS(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI8x16Eq(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI8x16Ne(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI8x16LtS(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI8x16LeS(Node* node) { UNIMPLEMENTED(); }
 
 void InstructionSelector::VisitI8x16ShrU(Node* node) { UNIMPLEMENTED(); }
 
+void InstructionSelector::VisitI8x16UConvertI16x8(Node* node) {
+  UNIMPLEMENTED();
+}
+
 void InstructionSelector::VisitI8x16AddSaturateU(Node* node) {
   UNIMPLEMENTED();
 }
 
 void InstructionSelector::VisitI8x16SubSaturateU(Node* node) {
   UNIMPLEMENTED();
 }
 
 void InstructionSelector::VisitI8x16MinU(Node* node) { UNIMPLEMENTED(); }
 
@@ skipping 442 matching lines @@
   return new (instruction_zone()) FrameStateDescriptor(
       instruction_zone(), state_info.type(), state_info.bailout_id(),
       state_info.state_combine(), parameters, locals, stack,
       state_info.shared_info(), outer_state);
 }
 
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8