MIPS[64]: Implement fill.df, copy_u.df, copy_s.df instructions in simulator

src/mips64/simulator-mips64.h

Index: src/mips64/simulator-mips64.h
diff --git a/src/mips64/simulator-mips64.h b/src/mips64/simulator-mips64.h
index 6c41ae111a3ede3659d6f362a280df1a3c3a5a44..216a736f4d13f78c5edd8511bc1d20b042854ab8 100644
--- a/src/mips64/simulator-mips64.h
+++ b/src/mips64/simulator-mips64.h
@@ -193,6 +193,54 @@ class Simulator {
     kNumFPURegisters
   };
 
+  // MSA registers
+  enum MSARegister {
+    w0,
+    w1,
+    w2,
+    w3,
+    w4,
+    w5,
+    w6,
+    w7,
+    w8,
+    w9,
+    w10,
+    w11,
+    w12,
+    w13,
+    w14,
+    w15,
+    w16,
+    w17,
+    w18,
+    w19,
+    w20,
+    w21,
+    w22,
+    w23,
+    w24,
+    w25,
+    w26,
+    w27,
+    w28,
+    w29,
+    w30,
+    w31,
+    kNumMSARegisters
+  };
+
+  const uint32_t kMsaI8Mask = ((3U << 24) | ((1 << 6) - 1));

[Ilija.Pavlovic1, 2017/04/20 13:13:46]

The same comments as for MIPS32 code.

[dusan.simicic, 2017/04/20 15:57:42]

I'll move constants in the same way as for mips32.

+  const uint32_t kMsaI5Mask = ((7U << 23) | ((1 << 6) - 1));
+  const uint32_t kMsaMI10Mask = (15U << 2);
+  const uint32_t kMsaBITMask = ((7U << 23) | ((1 << 6) - 1));
+  const uint32_t kMsaELMMask = (15U << 22);
+  const uint32_t kMsa3RMask = ((7U << 23) | ((1 << 6) - 1));
+  const uint32_t kMsa3RFMask = ((15U << 22) | ((1 << 6) - 1));
+  const uint32_t kMsaVECMask = (23U << 21);
+  const uint32_t kMsa2RMask = (7U << 18);
+  const uint32_t kMsa2RFMask = (15U << 17);
+
   explicit Simulator(Isolate* isolate);
   ~Simulator();
 
@@ -226,6 +274,10 @@ class Simulator {
   int32_t get_fpu_register_hi_word(int fpureg) const;
   float get_fpu_register_float(int fpureg) const;
   double get_fpu_register_double(int fpureg) const;
+  template <typename T>
+  void get_msa_register(int wreg, T* value);
+  template <typename T>
+  void set_msa_register(int wreg, const T* value);
   void set_fcsr_bit(uint32_t cc, bool value);
   bool test_fcsr_bit(uint32_t cc);
   bool set_fcsr_round_error(double original, double rounded);
@@ -315,6 +367,9 @@ class Simulator {
     WORD_DWORD
   };
 
+  // MSA Data Format
+  enum MSADataFormat { MSA_VECT = 0, MSA_BYTE, MSA_HALF, MSA_WORD, MSA_DWORD };
+
   // Read and write memory.
   inline uint32_t ReadBU(int64_t addr);
   inline int32_t ReadB(int64_t addr);
@@ -340,6 +395,8 @@ class Simulator {
   inline void DieOrDebug();
 
   void TraceRegWr(int64_t value, TraceType t = DWORD);
+  template <typename T>
+  void TraceMSARegWr(T* value, TraceType t);
   void TraceMemWr(int64_t addr, int64_t value, TraceType t);
   void TraceMemRd(int64_t addr, int64_t value, TraceType t = DWORD);
 
@@ -373,6 +430,19 @@ class Simulator {
 
   void DecodeTypeRegisterLRsType();
 
+  int DecodeMsaDataFormat();
+  void DecodeTypeMsaI8();
+  void DecodeTypeMsaI5();
+  void DecodeTypeMsaI10();
+  void DecodeTypeMsaELM();
+  void DecodeTypeMsaBIT();
+  void DecodeTypeMsaMI10();
+  void DecodeTypeMsa3R();
+  void DecodeTypeMsa3RF();
+  void DecodeTypeMsaVec();
+  void DecodeTypeMsa2R();
+  void DecodeTypeMsa2RF();
+
   // Executing is handled based on the instruction type.
   void DecodeTypeRegister();
 
@@ -393,6 +463,9 @@ class Simulator {
   inline int32_t fd_reg() const { return instr_.FdValue(); }
   inline int32_t sa() const { return instr_.SaValue(); }
   inline int32_t lsa_sa() const { return instr_.LsaSaValue(); }
+  inline int32_t ws_reg() const { return instr_.WsValue(); }
+  inline int32_t wt_reg() const { return instr_.WtValue(); }
+  inline int32_t wd_reg() const { return instr_.WdValue(); }
 
   inline void SetResult(const int32_t rd_reg, const int64_t alu_out) {
     set_register(rd_reg, alu_out);
@@ -512,7 +585,9 @@ class Simulator {
   // Registers.
   int64_t registers_[kNumSimuRegisters];
   // Coprocessor Registers.
-  int64_t FPUregisters_[kNumFPURegisters];
+  // Note: FPUregisters_[] array is increased to 64 * 8B = 32 * 16B in
+  // order to support MSA registers
+  int64_t FPUregisters_[kNumFPURegisters * 2];
   // FPU control register.
   uint32_t FCSR_;