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Side by Side Diff: src/compiler/x64/instruction-selector-x64.cc

Issue 2799863002: [Atomics] use TFJ builtins for atomic add, sub, and, or, and xor (Closed)
Patch Set: [Atomics] use TFJ builtins for atomic add, sub, and, or, and xor Created 3 years, 8 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include <algorithm> 5 #include <algorithm>
6 6
7 #include "src/base/adapters.h" 7 #include "src/base/adapters.h"
8 #include "src/compiler/instruction-selector-impl.h" 8 #include "src/compiler/instruction-selector-impl.h"
9 #include "src/compiler/node-matchers.h" 9 #include "src/compiler/node-matchers.h"
10 #include "src/compiler/node-properties.h" 10 #include "src/compiler/node-properties.h"
(...skipping 2287 matching lines...) Expand 10 before | Expand all | Expand 10 after
2298 InstructionCode code = opcode | AddressingModeField::encode(addressing_mode); 2298 InstructionCode code = opcode | AddressingModeField::encode(addressing_mode);
2299 Emit(code, 0, static_cast<InstructionOperand*>(nullptr), input_count, inputs); 2299 Emit(code, 0, static_cast<InstructionOperand*>(nullptr), input_count, inputs);
2300 } 2300 }
2301 2301
2302 void InstructionSelector::VisitAtomicExchange(Node* node) { 2302 void InstructionSelector::VisitAtomicExchange(Node* node) {
2303 X64OperandGenerator g(this); 2303 X64OperandGenerator g(this);
2304 Node* base = node->InputAt(0); 2304 Node* base = node->InputAt(0);
2305 Node* index = node->InputAt(1); 2305 Node* index = node->InputAt(1);
2306 Node* value = node->InputAt(2); 2306 Node* value = node->InputAt(2);
2307 2307
2308 MachineType type = AtomicExchangeRepresentationOf(node->op()); 2308 MachineType type = AtomicOpRepresentationOf(node->op());
2309 ArchOpcode opcode = kArchNop; 2309 ArchOpcode opcode = kArchNop;
2310 if (type == MachineType::Int8()) { 2310 if (type == MachineType::Int8()) {
2311 opcode = kAtomicExchangeInt8; 2311 opcode = kAtomicExchangeInt8;
2312 } else if (type == MachineType::Uint8()) { 2312 } else if (type == MachineType::Uint8()) {
2313 opcode = kAtomicExchangeUint8; 2313 opcode = kAtomicExchangeUint8;
2314 } else if (type == MachineType::Int16()) { 2314 } else if (type == MachineType::Int16()) {
2315 opcode = kAtomicExchangeInt16; 2315 opcode = kAtomicExchangeInt16;
2316 } else if (type == MachineType::Uint16()) { 2316 } else if (type == MachineType::Uint16()) {
2317 opcode = kAtomicExchangeUint16; 2317 opcode = kAtomicExchangeUint16;
2318 } else if (type == MachineType::Int32() || type == MachineType::Uint32()) { 2318 } else if (type == MachineType::Int32() || type == MachineType::Uint32()) {
2319 opcode = kAtomicExchangeWord32; 2319 opcode = kAtomicExchangeWord32;
2320 } else { 2320 } else {
2321 UNREACHABLE(); 2321 UNREACHABLE();
2322 return; 2322 return;
2323 } 2323 }
2324 InstructionOperand outputs[1]; 2324 InstructionOperand outputs[1];
2325 AddressingMode addressing_mode; 2325 AddressingMode addressing_mode;
2326 InstructionOperand inputs[4]; 2326 InstructionOperand inputs[3];
2327 size_t input_count = 0; 2327 size_t input_count = 0;
2328 inputs[input_count++] = g.UseUniqueRegister(value); 2328 inputs[input_count++] = g.UseUniqueRegister(value);
2329 inputs[input_count++] = g.UseUniqueRegister(base); 2329 inputs[input_count++] = g.UseUniqueRegister(base);
2330 if (g.CanBeImmediate(index)) { 2330 if (g.CanBeImmediate(index)) {
2331 inputs[input_count++] = g.UseImmediate(index); 2331 inputs[input_count++] = g.UseImmediate(index);
2332 addressing_mode = kMode_MRI; 2332 addressing_mode = kMode_MRI;
2333 } else { 2333 } else {
2334 inputs[input_count++] = g.UseUniqueRegister(index); 2334 inputs[input_count++] = g.UseUniqueRegister(index);
2335 addressing_mode = kMode_MR1; 2335 addressing_mode = kMode_MR1;
2336 } 2336 }
2337 outputs[0] = g.DefineSameAsFirst(node); 2337 outputs[0] = g.DefineSameAsFirst(node);
2338 InstructionCode code = opcode | AddressingModeField::encode(addressing_mode); 2338 InstructionCode code = opcode | AddressingModeField::encode(addressing_mode);
2339 Emit(code, 1, outputs, input_count, inputs); 2339 Emit(code, 1, outputs, input_count, inputs);
2340 } 2340 }
2341 2341
2342 void InstructionSelector::VisitAtomicCompareExchange(Node* node) { 2342 void InstructionSelector::VisitAtomicCompareExchange(Node* node) {
2343 X64OperandGenerator g(this); 2343 X64OperandGenerator g(this);
2344 Node* base = node->InputAt(0); 2344 Node* base = node->InputAt(0);
2345 Node* index = node->InputAt(1); 2345 Node* index = node->InputAt(1);
2346 Node* old_value = node->InputAt(2); 2346 Node* old_value = node->InputAt(2);
2347 Node* new_value = node->InputAt(3); 2347 Node* new_value = node->InputAt(3);
2348 2348
2349 MachineType type = AtomicCompareExchangeRepresentationOf(node->op()); 2349 MachineType type = AtomicOpRepresentationOf(node->op());
2350 ArchOpcode opcode = kArchNop; 2350 ArchOpcode opcode = kArchNop;
2351 if (type == MachineType::Int8()) { 2351 if (type == MachineType::Int8()) {
2352 opcode = kAtomicCompareExchangeInt8; 2352 opcode = kAtomicCompareExchangeInt8;
2353 } else if (type == MachineType::Uint8()) { 2353 } else if (type == MachineType::Uint8()) {
2354 opcode = kAtomicCompareExchangeUint8; 2354 opcode = kAtomicCompareExchangeUint8;
2355 } else if (type == MachineType::Int16()) { 2355 } else if (type == MachineType::Int16()) {
2356 opcode = kAtomicCompareExchangeInt16; 2356 opcode = kAtomicCompareExchangeInt16;
2357 } else if (type == MachineType::Uint16()) { 2357 } else if (type == MachineType::Uint16()) {
2358 opcode = kAtomicCompareExchangeUint16; 2358 opcode = kAtomicCompareExchangeUint16;
2359 } else if (type == MachineType::Int32() || type == MachineType::Uint32()) { 2359 } else if (type == MachineType::Int32() || type == MachineType::Uint32()) {
(...skipping 14 matching lines...) Expand all
2374 addressing_mode = kMode_MRI; 2374 addressing_mode = kMode_MRI;
2375 } else { 2375 } else {
2376 inputs[input_count++] = g.UseUniqueRegister(index); 2376 inputs[input_count++] = g.UseUniqueRegister(index);
2377 addressing_mode = kMode_MR1; 2377 addressing_mode = kMode_MR1;
2378 } 2378 }
2379 outputs[0] = g.DefineAsFixed(node, rax); 2379 outputs[0] = g.DefineAsFixed(node, rax);
2380 InstructionCode code = opcode | AddressingModeField::encode(addressing_mode); 2380 InstructionCode code = opcode | AddressingModeField::encode(addressing_mode);
2381 Emit(code, 1, outputs, input_count, inputs); 2381 Emit(code, 1, outputs, input_count, inputs);
2382 } 2382 }
2383 2383
2384 void InstructionSelector::VisitAtomicBinaryOperation(
2385 Node* node, ArchOpcode int8_op, ArchOpcode uint8_op, ArchOpcode int16_op,
2386 ArchOpcode uint16_op, ArchOpcode word32_op) {
2387 X64OperandGenerator g(this);
2388 Node* base = node->InputAt(0);
2389 Node* index = node->InputAt(1);
2390 Node* value = node->InputAt(2);
2391
2392 MachineType type = AtomicOpRepresentationOf(node->op());
2393 ArchOpcode opcode = kArchNop;
2394 if (type == MachineType::Int8()) {
2395 opcode = int8_op;
2396 } else if (type == MachineType::Uint8()) {
2397 opcode = uint8_op;
2398 } else if (type == MachineType::Int16()) {
2399 opcode = int16_op;
2400 } else if (type == MachineType::Uint16()) {
2401 opcode = uint16_op;
2402 } else if (type == MachineType::Int32() || type == MachineType::Uint32()) {
2403 opcode = word32_op;
2404 } else {
2405 UNREACHABLE();
2406 return;
2407 }
2408 InstructionOperand outputs[1];
2409 AddressingMode addressing_mode;
2410 InstructionOperand inputs[3];
2411 size_t input_count = 0;
2412 inputs[input_count++] = g.UseUniqueRegister(value);
2413 inputs[input_count++] = g.UseUniqueRegister(base);
2414 if (g.CanBeImmediate(index)) {
2415 inputs[input_count++] = g.UseImmediate(index);
2416 addressing_mode = kMode_MRI;
2417 } else {
2418 inputs[input_count++] = g.UseUniqueRegister(index);
2419 addressing_mode = kMode_MR1;
2420 }
2421 outputs[0] = g.DefineAsFixed(node, rax);
2422 InstructionOperand temp[1];
2423 temp[0] = g.TempRegister();
2424 InstructionCode code = opcode | AddressingModeField::encode(addressing_mode);
2425 Emit(code, 1, outputs, input_count, inputs, 1, temp);
2426 }
2427
2428 #define VISIT_ATOMIC_BINOP(op) \
2429 void InstructionSelector::VisitAtomic##op(Node* node) { \
2430 VisitAtomicBinaryOperation(node, kAtomic##op##Int8, kAtomic##op##Uint8, \
2431 kAtomic##op##Int16, kAtomic##op##Uint16, \
2432 kAtomic##op##Word32); \
2433 }
2434 VISIT_ATOMIC_BINOP(Add)
2435 VISIT_ATOMIC_BINOP(Sub)
2436 VISIT_ATOMIC_BINOP(And)
2437 VISIT_ATOMIC_BINOP(Or)
2438 VISIT_ATOMIC_BINOP(Xor)
2439 #undef VISIT_ATOMIC_BINOP
2440
2384 #define SIMD_TYPES(V) V(I32x4) 2441 #define SIMD_TYPES(V) V(I32x4)
2385 2442
2386 #define SIMD_ZERO_OP_LIST(V) \ 2443 #define SIMD_ZERO_OP_LIST(V) \
2387 V(S128Zero) \ 2444 V(S128Zero) \
2388 V(S1x4Zero) \ 2445 V(S1x4Zero) \
2389 V(S1x8Zero) \ 2446 V(S1x8Zero) \
2390 V(S1x16Zero) 2447 V(S1x16Zero)
2391 2448
2392 #define SIMD_SHIFT_OPCODES(V) \ 2449 #define SIMD_SHIFT_OPCODES(V) \
2393 V(I32x4Shl) \ 2450 V(I32x4Shl) \
(...skipping 109 matching lines...) Expand 10 before | Expand all | Expand 10 after
2503 // static 2560 // static
2504 MachineOperatorBuilder::AlignmentRequirements 2561 MachineOperatorBuilder::AlignmentRequirements
2505 InstructionSelector::AlignmentRequirements() { 2562 InstructionSelector::AlignmentRequirements() {
2506 return MachineOperatorBuilder::AlignmentRequirements:: 2563 return MachineOperatorBuilder::AlignmentRequirements::
2507 FullUnalignedAccessSupport(); 2564 FullUnalignedAccessSupport();
2508 } 2565 }
2509 2566
2510 } // namespace compiler 2567 } // namespace compiler
2511 } // namespace internal 2568 } // namespace internal
2512 } // namespace v8 2569 } // namespace v8
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