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Side by Side Diff: src/compiler/ia32/instruction-selector-ia32.cc

Issue 2799863002: [Atomics] use TFJ builtins for atomic add, sub, and, or, and xor (Closed)
Patch Set: [Atomics] use TFJ builtins for atomic add, sub, and, or, and xor Created 3 years, 8 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "src/base/adapters.h" 5 #include "src/base/adapters.h"
6 #include "src/compiler/instruction-selector-impl.h" 6 #include "src/compiler/instruction-selector-impl.h"
7 #include "src/compiler/node-matchers.h" 7 #include "src/compiler/node-matchers.h"
8 #include "src/compiler/node-properties.h" 8 #include "src/compiler/node-properties.h"
9 9
10 namespace v8 { 10 namespace v8 {
(...skipping 1706 matching lines...) Expand 10 before | Expand all | Expand 10 after
1717 case MachineRepresentation::kWord32: 1717 case MachineRepresentation::kWord32:
1718 opcode = kAtomicExchangeWord32; 1718 opcode = kAtomicExchangeWord32;
1719 break; 1719 break;
1720 default: 1720 default:
1721 UNREACHABLE(); 1721 UNREACHABLE();
1722 break; 1722 break;
1723 } 1723 }
1724 AddressingMode addressing_mode; 1724 AddressingMode addressing_mode;
1725 InstructionOperand inputs[4]; 1725 InstructionOperand inputs[4];
1726 size_t input_count = 0; 1726 size_t input_count = 0;
1727 inputs[input_count++] = g.UseUniqueRegister(value); 1727 if (rep == MachineRepresentation::kWord8) {
1728 inputs[input_count++] = g.UseByteRegister(value);
1729 } else {
1730 inputs[input_count++] = g.UseUniqueRegister(value);
1731 }
1728 inputs[input_count++] = g.UseUniqueRegister(base); 1732 inputs[input_count++] = g.UseUniqueRegister(base);
1729 if (g.CanBeImmediate(index)) { 1733 if (g.CanBeImmediate(index)) {
1730 inputs[input_count++] = g.UseImmediate(index); 1734 inputs[input_count++] = g.UseImmediate(index);
1731 addressing_mode = kMode_MRI; 1735 addressing_mode = kMode_MRI;
1732 } else { 1736 } else {
1733 inputs[input_count++] = g.UseUniqueRegister(index); 1737 inputs[input_count++] = g.UseUniqueRegister(index);
1734 addressing_mode = kMode_MR1; 1738 addressing_mode = kMode_MR1;
1735 } 1739 }
1736 InstructionCode code = opcode | AddressingModeField::encode(addressing_mode); 1740 InstructionCode code = opcode | AddressingModeField::encode(addressing_mode);
1737 Emit(code, 0, nullptr, input_count, inputs); 1741 Emit(code, 0, nullptr, input_count, inputs);
1738 } 1742 }
1739 1743
1740 void InstructionSelector::VisitAtomicExchange(Node* node) { 1744 void InstructionSelector::VisitAtomicExchange(Node* node) {
1741 IA32OperandGenerator g(this); 1745 IA32OperandGenerator g(this);
1742 Node* base = node->InputAt(0); 1746 Node* base = node->InputAt(0);
1743 Node* index = node->InputAt(1); 1747 Node* index = node->InputAt(1);
1744 Node* value = node->InputAt(2); 1748 Node* value = node->InputAt(2);
1745 1749
1746 MachineType type = AtomicExchangeRepresentationOf(node->op()); 1750 MachineType type = AtomicOpRepresentationOf(node->op());
1747 ArchOpcode opcode = kArchNop; 1751 ArchOpcode opcode = kArchNop;
1748 if (type == MachineType::Int8()) { 1752 if (type == MachineType::Int8()) {
1749 opcode = kAtomicExchangeInt8; 1753 opcode = kAtomicExchangeInt8;
1750 } else if (type == MachineType::Uint8()) { 1754 } else if (type == MachineType::Uint8()) {
1751 opcode = kAtomicExchangeUint8; 1755 opcode = kAtomicExchangeUint8;
1752 } else if (type == MachineType::Int16()) { 1756 } else if (type == MachineType::Int16()) {
1753 opcode = kAtomicExchangeInt16; 1757 opcode = kAtomicExchangeInt16;
1754 } else if (type == MachineType::Uint16()) { 1758 } else if (type == MachineType::Uint16()) {
1755 opcode = kAtomicExchangeUint16; 1759 opcode = kAtomicExchangeUint16;
1756 } else if (type == MachineType::Int32() || type == MachineType::Uint32()) { 1760 } else if (type == MachineType::Int32() || type == MachineType::Uint32()) {
1757 opcode = kAtomicExchangeWord32; 1761 opcode = kAtomicExchangeWord32;
1758 } else { 1762 } else {
1759 UNREACHABLE(); 1763 UNREACHABLE();
1760 return; 1764 return;
1761 } 1765 }
1762 InstructionOperand outputs[1]; 1766 InstructionOperand outputs[1];
1763 AddressingMode addressing_mode; 1767 AddressingMode addressing_mode;
1764 InstructionOperand inputs[4]; 1768 InstructionOperand inputs[3];
1765 size_t input_count = 0; 1769 size_t input_count = 0;
1766 inputs[input_count++] = g.UseUniqueRegister(value); 1770 if (type == MachineType::Int8() || type == MachineType::Uint8()) {
1771 inputs[input_count++] = g.UseFixed(value, edx);
1772 } else {
1773 inputs[input_count++] = g.UseUniqueRegister(value);
1774 }
1767 inputs[input_count++] = g.UseUniqueRegister(base); 1775 inputs[input_count++] = g.UseUniqueRegister(base);
1768 if (g.CanBeImmediate(index)) { 1776 if (g.CanBeImmediate(index)) {
1769 inputs[input_count++] = g.UseImmediate(index); 1777 inputs[input_count++] = g.UseImmediate(index);
1770 addressing_mode = kMode_MRI; 1778 addressing_mode = kMode_MRI;
1771 } else { 1779 } else {
1772 inputs[input_count++] = g.UseUniqueRegister(index); 1780 inputs[input_count++] = g.UseUniqueRegister(index);
1773 addressing_mode = kMode_MR1; 1781 addressing_mode = kMode_MR1;
1774 } 1782 }
1775 outputs[0] = g.DefineSameAsFirst(node); 1783 if (type == MachineType::Int8() || type == MachineType::Uint8()) {
1784 // Using DefineSameAsFirst requires the register to be unallocated.
1785 outputs[0] = g.DefineAsFixed(node, edx);
1786 } else {
1787 outputs[0] = g.DefineSameAsFirst(node);
1788 }
1776 InstructionCode code = opcode | AddressingModeField::encode(addressing_mode); 1789 InstructionCode code = opcode | AddressingModeField::encode(addressing_mode);
1777 Emit(code, 1, outputs, input_count, inputs); 1790 Emit(code, 1, outputs, input_count, inputs);
1778 } 1791 }
1779 1792
1780 void InstructionSelector::VisitAtomicCompareExchange(Node* node) { 1793 void InstructionSelector::VisitAtomicCompareExchange(Node* node) {
1781 IA32OperandGenerator g(this); 1794 IA32OperandGenerator g(this);
1782 Node* base = node->InputAt(0); 1795 Node* base = node->InputAt(0);
1783 Node* index = node->InputAt(1); 1796 Node* index = node->InputAt(1);
1784 Node* old_value = node->InputAt(2); 1797 Node* old_value = node->InputAt(2);
1785 Node* new_value = node->InputAt(3); 1798 Node* new_value = node->InputAt(3);
1786 1799
1787 MachineType type = AtomicCompareExchangeRepresentationOf(node->op()); 1800 MachineType type = AtomicOpRepresentationOf(node->op());
1788 ArchOpcode opcode = kArchNop; 1801 ArchOpcode opcode = kArchNop;
1789 if (type == MachineType::Int8()) { 1802 if (type == MachineType::Int8()) {
1790 opcode = kAtomicCompareExchangeInt8; 1803 opcode = kAtomicCompareExchangeInt8;
1791 } else if (type == MachineType::Uint8()) { 1804 } else if (type == MachineType::Uint8()) {
1792 opcode = kAtomicCompareExchangeUint8; 1805 opcode = kAtomicCompareExchangeUint8;
1793 } else if (type == MachineType::Int16()) { 1806 } else if (type == MachineType::Int16()) {
1794 opcode = kAtomicCompareExchangeInt16; 1807 opcode = kAtomicCompareExchangeInt16;
1795 } else if (type == MachineType::Uint16()) { 1808 } else if (type == MachineType::Uint16()) {
1796 opcode = kAtomicCompareExchangeUint16; 1809 opcode = kAtomicCompareExchangeUint16;
1797 } else if (type == MachineType::Int32() || type == MachineType::Uint32()) { 1810 } else if (type == MachineType::Int32() || type == MachineType::Uint32()) {
1798 opcode = kAtomicCompareExchangeWord32; 1811 opcode = kAtomicCompareExchangeWord32;
1799 } else { 1812 } else {
1800 UNREACHABLE(); 1813 UNREACHABLE();
1801 return; 1814 return;
1802 } 1815 }
1803 InstructionOperand outputs[1]; 1816 InstructionOperand outputs[1];
1804 AddressingMode addressing_mode; 1817 AddressingMode addressing_mode;
1805 InstructionOperand inputs[4]; 1818 InstructionOperand inputs[4];
1806 size_t input_count = 0; 1819 size_t input_count = 0;
1807 inputs[input_count++] = g.UseFixed(old_value, eax); 1820 inputs[input_count++] = g.UseFixed(old_value, eax);
1808 inputs[input_count++] = g.UseUniqueRegister(new_value); 1821 if (type == MachineType::Int8() || type == MachineType::Uint8()) {
1822 inputs[input_count++] = g.UseByteRegister(new_value);
1823 } else {
1824 inputs[input_count++] = g.UseUniqueRegister(new_value);
1825 }
1809 inputs[input_count++] = g.UseUniqueRegister(base); 1826 inputs[input_count++] = g.UseUniqueRegister(base);
1810 if (g.CanBeImmediate(index)) { 1827 if (g.CanBeImmediate(index)) {
1811 inputs[input_count++] = g.UseImmediate(index); 1828 inputs[input_count++] = g.UseImmediate(index);
1812 addressing_mode = kMode_MRI; 1829 addressing_mode = kMode_MRI;
1813 } else { 1830 } else {
1814 inputs[input_count++] = g.UseUniqueRegister(index); 1831 inputs[input_count++] = g.UseUniqueRegister(index);
1815 addressing_mode = kMode_MR1; 1832 addressing_mode = kMode_MR1;
1816 } 1833 }
1817 outputs[0] = g.DefineAsFixed(node, eax); 1834 outputs[0] = g.DefineAsFixed(node, eax);
1818 InstructionCode code = opcode | AddressingModeField::encode(addressing_mode); 1835 InstructionCode code = opcode | AddressingModeField::encode(addressing_mode);
1819 Emit(code, 1, outputs, input_count, inputs); 1836 Emit(code, 1, outputs, input_count, inputs);
1820 } 1837 }
1821 1838
1839 void InstructionSelector::VisitAtomicBinaryOperation(
1840 Node* node, ArchOpcode int8_op, ArchOpcode uint8_op, ArchOpcode int16_op,
1841 ArchOpcode uint16_op, ArchOpcode word32_op) {
1842 IA32OperandGenerator g(this);
1843 Node* base = node->InputAt(0);
1844 Node* index = node->InputAt(1);
1845 Node* value = node->InputAt(2);
1846
1847 MachineType type = AtomicOpRepresentationOf(node->op());
1848 ArchOpcode opcode = kArchNop;
1849 if (type == MachineType::Int8()) {
1850 opcode = int8_op;
1851 } else if (type == MachineType::Uint8()) {
1852 opcode = uint8_op;
1853 } else if (type == MachineType::Int16()) {
1854 opcode = int16_op;
1855 } else if (type == MachineType::Uint16()) {
1856 opcode = uint16_op;
1857 } else if (type == MachineType::Int32() || type == MachineType::Uint32()) {
1858 opcode = word32_op;
1859 } else {
1860 UNREACHABLE();
1861 return;
1862 }
1863 InstructionOperand outputs[1];
1864 AddressingMode addressing_mode;
1865 InstructionOperand inputs[3];
1866 size_t input_count = 0;
1867 if (type == MachineType::Int8() || type == MachineType::Uint8()) {
1868 inputs[input_count++] = g.UseByteRegister(value);
1869 } else {
1870 inputs[input_count++] = g.UseUniqueRegister(value);
1871 }
1872 inputs[input_count++] = g.UseUniqueRegister(base);
1873 if (g.CanBeImmediate(index)) {
1874 inputs[input_count++] = g.UseImmediate(index);
1875 addressing_mode = kMode_MRI;
1876 } else {
1877 inputs[input_count++] = g.UseUniqueRegister(index);
1878 addressing_mode = kMode_MR1;
1879 }
1880 outputs[0] = g.DefineAsFixed(node, eax);
1881 InstructionOperand temp[1];
1882 temp[0] = g.TempRegister();
1883 InstructionCode code = opcode | AddressingModeField::encode(addressing_mode);
1884 Emit(code, 1, outputs, input_count, inputs, 1, temp);
1885 }
1886
1887 #define VISIT_ATOMIC_BINOP(op) \
1888 void InstructionSelector::VisitAtomic##op(Node* node) { \
1889 VisitAtomicBinaryOperation(node, kAtomic##op##Int8, kAtomic##op##Uint8, \
1890 kAtomic##op##Int16, kAtomic##op##Uint16, \
1891 kAtomic##op##Word32); \
1892 }
1893 VISIT_ATOMIC_BINOP(Add)
1894 VISIT_ATOMIC_BINOP(Sub)
1895 VISIT_ATOMIC_BINOP(And)
1896 VISIT_ATOMIC_BINOP(Or)
1897 VISIT_ATOMIC_BINOP(Xor)
1898 #undef VISIT_ATOMIC_BINOP
1899
1822 void InstructionSelector::VisitI32x4Splat(Node* node) { 1900 void InstructionSelector::VisitI32x4Splat(Node* node) {
1823 VisitRO(this, node, kIA32I32x4Splat); 1901 VisitRO(this, node, kIA32I32x4Splat);
1824 } 1902 }
1825 1903
1826 void InstructionSelector::VisitI32x4ExtractLane(Node* node) { 1904 void InstructionSelector::VisitI32x4ExtractLane(Node* node) {
1827 IA32OperandGenerator g(this); 1905 IA32OperandGenerator g(this);
1828 int32_t lane = OpParameter<int32_t>(node); 1906 int32_t lane = OpParameter<int32_t>(node);
1829 Emit(kIA32I32x4ExtractLane, g.DefineAsRegister(node), 1907 Emit(kIA32I32x4ExtractLane, g.DefineAsRegister(node),
1830 g.UseRegister(node->InputAt(0)), g.UseImmediate(lane)); 1908 g.UseRegister(node->InputAt(0)), g.UseImmediate(lane));
1831 } 1909 }
(...skipping 39 matching lines...) Expand 10 before | Expand all | Expand 10 after
1871 // static 1949 // static
1872 MachineOperatorBuilder::AlignmentRequirements 1950 MachineOperatorBuilder::AlignmentRequirements
1873 InstructionSelector::AlignmentRequirements() { 1951 InstructionSelector::AlignmentRequirements() {
1874 return MachineOperatorBuilder::AlignmentRequirements:: 1952 return MachineOperatorBuilder::AlignmentRequirements::
1875 FullUnalignedAccessSupport(); 1953 FullUnalignedAccessSupport();
1876 } 1954 }
1877 1955
1878 } // namespace compiler 1956 } // namespace compiler
1879 } // namespace internal 1957 } // namespace internal
1880 } // namespace v8 1958 } // namespace v8
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