[ARM] Implement D-register versions of vzip, vuzp, and vtrn.

src/arm/disasm-arm.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 // A Disassembler object is used to disassemble a block of code instruction by
 // instruction. The default implementation of the NameConverter object can be
 // overriden to modify register names or to do symbol lookup on addresses.
 //
 // The example below will disassemble a block of code and print it to stdout.
 //
@@ skipping 2149 matching lines @@
       if ((instr->Bits(18, 16) == 0) && (instr->Bits(11, 6) == 0x28) &&
           (instr->Bit(4) == 1)) {
         // vmovl unsigned
         if ((instr->VdValue() & 1) != 0) Unknown(instr);
         int Vd = (instr->Bit(22) << 3) | (instr->VdValue() >> 1);
         int Vm = (instr->Bit(5) << 4) | instr->VmValue();
         int imm3 = instr->Bits(21, 19);
         out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
                                     "vmovl.u%d q%d, d%d", imm3 * 8, Vd, Vm);
       } else if (instr->Opc1Value() == 7 && instr->Bit(4) == 0) {
-        if (instr->Bits(17, 16) == 0x2 && instr->Bits(11, 7) == 0) {
-          if (instr->Bit(6) == 0) {
-            int Vd = instr->VFPDRegValue(kDoublePrecision);
-            int Vm = instr->VFPMRegValue(kDoublePrecision);
-            out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
-                                        "vswp d%d, d%d", Vd, Vm);
-          } else {
-            int Vd = instr->VFPDRegValue(kSimd128Precision);
-            int Vm = instr->VFPMRegValue(kSimd128Precision);
-            out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
-                                        "vswp q%d, q%d", Vd, Vm);
-          }
-        } else if (instr->Bits(11, 7) == 0x18) {
+        if (instr->Bits(11, 7) == 0x18) {
           int Vd = instr->VFPDRegValue(kSimd128Precision);
           int Vm = instr->VFPMRegValue(kDoublePrecision);
           int index = instr->Bit(19);
           out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
                                       "vdup q%d, d%d[%d]", Vd, Vm, index);
-        } else if (instr->Bits(19, 16) == 0 && instr->Bits(11, 6) == 0x17) {
-          int Vd = instr->VFPDRegValue(kSimd128Precision);
-          int Vm = instr->VFPMRegValue(kSimd128Precision);
-          out_buffer_pos_ +=
-              SNPrintF(out_buffer_ + out_buffer_pos_, "vmvn q%d, q%d", Vd, Vm);
-        } else if (instr->Bits(19, 16) == 0xB && instr->Bits(11, 9) == 0x3 &&
-                   instr->Bit(6) == 1) {
-          int Vd = instr->VFPDRegValue(kSimd128Precision);
-          int Vm = instr->VFPMRegValue(kSimd128Precision);
-          const char* suffix = nullptr;
-          int op = instr->Bits(8, 7);
-          switch (op) {
-            case 0:
-              suffix = "f32.s32";
-              break;
-            case 1:
-              suffix = "f32.u32";
-              break;
-            case 2:
-              suffix = "s32.f32";
-              break;
-            case 3:
-              suffix = "u32.f32";
-              break;
-          }
-          out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
-                                      "vcvt.%s q%d, q%d", suffix, Vd, Vm);
         } else if (instr->Bits(11, 10) == 0x2) {
           int Vd = instr->VFPDRegValue(kDoublePrecision);
           int Vn = instr->VFPNRegValue(kDoublePrecision);
           int Vm = instr->VFPMRegValue(kDoublePrecision);
           int len = instr->Bits(9, 8);
           NeonListOperand list(DwVfpRegister::from_code(Vn), len + 1);
           out_buffer_pos_ +=
               SNPrintF(out_buffer_ + out_buffer_pos_, "%s d%d, ",
                        instr->Bit(6) == 0 ? "vtbl.8" : "vtbx.8", Vd);
           FormatNeonList(Vn, list.type());
           Print(", ");
           PrintDRegister(Vm);
-        } else if (instr->Bits(17, 16) == 0x2 && instr->Bits(11, 8) == 0x1 &&
-                   instr->Bit(6) == 1) {
-          int Vd = instr->VFPDRegValue(kSimd128Precision);
-          int Vm = instr->VFPMRegValue(kSimd128Precision);
-          int size = kBitsPerByte * (1 << instr->Bits(19, 18));
-          const char* op = instr->Bit(7) != 0 ? "vzip" : "vuzp";
-          // vzip/vuzp.<size> Qd, Qm.
-          out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
-                                      "%s.%d q%d, q%d", op, size, Vd, Vm);
-        } else if (instr->Bits(17, 16) == 0 && instr->Bits(11, 9) == 0 &&
-                   instr->Bit(6) == 1) {
-          int Vd = instr->VFPDRegValue(kSimd128Precision);
-          int Vm = instr->VFPMRegValue(kSimd128Precision);
-          int size = kBitsPerByte * (1 << instr->Bits(19, 18));
-          int op = kBitsPerByte
-                   << (static_cast<int>(Neon64) - instr->Bits(8, 7));
-          // vrev<op>.<size> Qd, Qm.
-          out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
-                                      "vrev%d.%d q%d, q%d", op, size, Vd, Vm);
-        } else if (instr->Bits(17, 16) == 0x2 && instr->Bits(11, 6) == 0x3) {
-          int Vd = instr->VFPDRegValue(kSimd128Precision);
-          int Vm = instr->VFPMRegValue(kSimd128Precision);
-          int size = kBitsPerByte * (1 << instr->Bits(19, 18));
-          // vtrn.<size> Qd, Qm.
-          out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
-                                      "vtrn.%d q%d, q%d", size, Vd, Vm);
-        } else if (instr->Bits(17, 16) == 0x1 && instr->Bit(11) == 0 &&
-                   instr->Bit(6) == 1) {
-          int Vd = instr->VFPDRegValue(kSimd128Precision);
-          int Vm = instr->VFPMRegValue(kSimd128Precision);
-          int size = kBitsPerByte * (1 << instr->Bits(19, 18));
-          char type = instr->Bit(10) != 0 ? 'f' : 's';
-          if (instr->Bits(9, 6) == 0xd) {
-            // vabs<type>.<size> Qd, Qm.
-            out_buffer_pos_ +=
-                SNPrintF(out_buffer_ + out_buffer_pos_, "vabs.%c%d q%d, q%d",
-                         type, size, Vd, Vm);
-          } else if (instr->Bits(9, 6) == 0xf) {
-            // vneg<type>.<size> Qd, Qm.
-            out_buffer_pos_ +=
-                SNPrintF(out_buffer_ + out_buffer_pos_, "vneg.%c%d q%d, q%d",
-                         type, size, Vd, Vm);
-          } else {
-            Unknown(instr);
-          }
-        } else if (instr->Bits(19, 18) == 0x2 && instr->Bits(11, 8) == 0x5 &&
-                   instr->Bit(6) == 1) {
-          // vrecpe/vrsqrte.f32 Qd, Qm.
-          int Vd = instr->VFPDRegValue(kSimd128Precision);
-          int Vm = instr->VFPMRegValue(kSimd128Precision);
-          const char* op = instr->Bit(7) == 0 ? "vrecpe" : "vrsqrte";
-          out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
-                                      "%s.f32 q%d, q%d", op, Vd, Vm);
         } else if (instr->Bits(17, 16) == 0x2 && instr->Bits(11, 8) == 0x2 &&
                    instr->Bits(7, 6) != 0) {
           // vqmovn.<type><size> Dd, Qm.
           int Vd = instr->VFPDRegValue(kDoublePrecision);
           int Vm = instr->VFPMRegValue(kSimd128Precision);
           char type = instr->Bit(6) != 0 ? 'u' : 's';
           int size = 2 * kBitsPerByte * (1 << instr->Bits(19, 18));
           out_buffer_pos_ +=
               SNPrintF(out_buffer_ + out_buffer_pos_, "vqmovn.%c%i d%d, q%d",
                        type, size, Vd, Vm);
         } else {
-          Unknown(instr);
+          int Vd, Vm;
+          if (instr->Bit(6) == 0) {
+            Vd = instr->VFPDRegValue(kDoublePrecision);
+            Vm = instr->VFPMRegValue(kDoublePrecision);
+          } else {
+            Vd = instr->VFPDRegValue(kSimd128Precision);
+            Vm = instr->VFPMRegValue(kSimd128Precision);
+          }
+          if (instr->Bits(17, 16) == 0x2 && instr->Bits(11, 7) == 0) {
+            if (instr->Bit(6) == 0) {
+              out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
+                                          "vswp d%d, d%d", Vd, Vm);
+            } else {
+              out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
+                                          "vswp q%d, q%d", Vd, Vm);
+            }
+          } else if (instr->Bits(19, 16) == 0 && instr->Bits(11, 6) == 0x17) {
+            out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
+                                        "vmvn q%d, q%d", Vd, Vm);
+          } else if (instr->Bits(19, 16) == 0xB && instr->Bits(11, 9) == 0x3 &&
+                     instr->Bit(6) == 1) {
+            const char* suffix = nullptr;
+            int op = instr->Bits(8, 7);
+            switch (op) {
+              case 0:
+                suffix = "f32.s32";
+                break;
+              case 1:
+                suffix = "f32.u32";
+                break;
+              case 2:
+                suffix = "s32.f32";
+                break;
+              case 3:
+                suffix = "u32.f32";
+                break;
+            }
+            out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
+                                        "vcvt.%s q%d, q%d", suffix, Vd, Vm);
+          } else if (instr->Bits(17, 16) == 0x2 && instr->Bits(11, 8) == 0x1) {
+            int size = kBitsPerByte * (1 << instr->Bits(19, 18));
+            const char* op = instr->Bit(7) != 0 ? "vzip" : "vuzp";
+            if (instr->Bit(6) == 0) {
+              // vzip/vuzp.<size> Dd, Dm.
+              out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
+                                          "%s.%d d%d, d%d", op, size, Vd, Vm);
+            } else {
+              // vzip/vuzp.<size> Qd, Qm.
+              out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
+                                          "%s.%d q%d, q%d", op, size, Vd, Vm);
+            }
+          } else if (instr->Bits(17, 16) == 0 && instr->Bits(11, 9) == 0 &&
+                     instr->Bit(6) == 1) {
+            int size = kBitsPerByte * (1 << instr->Bits(19, 18));
+            int op = kBitsPerByte
+                     << (static_cast<int>(Neon64) - instr->Bits(8, 7));
+            // vrev<op>.<size> Qd, Qm.
+            out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
+                                        "vrev%d.%d q%d, q%d", op, size, Vd, Vm);
+          } else if (instr->Bits(17, 16) == 0x2 && instr->Bits(11, 7) == 0x1) {
+            int size = kBitsPerByte * (1 << instr->Bits(19, 18));
+            if (instr->Bit(6) == 0) {
+              // vtrn.<size> Dd, Dm.
+              out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
+                                          "vtrn.%d d%d, d%d", size, Vd, Vm);
+            } else {
+              // vtrn.<size> Qd, Qm.
+              out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
+                                          "vtrn.%d q%d, q%d", size, Vd, Vm);
+            }
+          } else if (instr->Bits(17, 16) == 0x1 && instr->Bit(11) == 0 &&
+                     instr->Bit(6) == 1) {
+            int size = kBitsPerByte * (1 << instr->Bits(19, 18));
+            char type = instr->Bit(10) != 0 ? 'f' : 's';
+            if (instr->Bits(9, 6) == 0xd) {
+              // vabs<type>.<size> Qd, Qm.
+              out_buffer_pos_ +=
+                  SNPrintF(out_buffer_ + out_buffer_pos_, "vabs.%c%d q%d, q%d",
+                           type, size, Vd, Vm);
+            } else if (instr->Bits(9, 6) == 0xf) {
+              // vneg<type>.<size> Qd, Qm.
+              out_buffer_pos_ +=
+                  SNPrintF(out_buffer_ + out_buffer_pos_, "vneg.%c%d q%d, q%d",
+                           type, size, Vd, Vm);
+            } else {
+              Unknown(instr);
+            }
+          } else if (instr->Bits(19, 18) == 0x2 && instr->Bits(11, 8) == 0x5 &&
+                     instr->Bit(6) == 1) {
+            // vrecpe/vrsqrte.f32 Qd, Qm.
+            const char* op = instr->Bit(7) == 0 ? "vrecpe" : "vrsqrte";
+            out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
+                                        "%s.f32 q%d, q%d", op, Vd, Vm);
+          } else {
+            Unknown(instr);
+          }
         }
       } else if (instr->Bits(11, 7) == 0 && instr->Bit(4) == 1 &&
                  instr->Bit(6) == 1) {
         // vshr.u<size> Qd, Qm, shift
         int size = base::bits::RoundDownToPowerOfTwo32(instr->Bits(21, 16));
         int shift = 2 * size - instr->Bits(21, 16);
         int Vd = instr->VFPDRegValue(kSimd128Precision);
         int Vm = instr->VFPMRegValue(kSimd128Precision);
         out_buffer_pos_ +=
             SNPrintF(out_buffer_ + out_buffer_pos_, "vshr.u%d q%d, q%d, #%d",
@@ skipping 336 matching lines @@
     pc += d.InstructionDecode(buffer, pc);
     v8::internal::PrintF(f, "%p    %08x      %s\n", static_cast<void*>(prev_pc),
                          *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
   }
 }
 
 
 }  // namespace disasm
 
 #endif  // V8_TARGET_ARCH_ARM