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Issue 2797923006: [ARM] Implement D-register versions of vzip, vuzp, and vtrn. (Closed)
Patch Set: Remove tests for vzip.32 / vuzp.32 - these are pseudo ops for vtrn.32. Created 3 years, 8 months ago
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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. 1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved. 2 // All Rights Reserved.
3 // 3 //
4 // Redistribution and use in source and binary forms, with or without 4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions 5 // modification, are permitted provided that the following conditions
6 // are met: 6 // are met:
7 // 7 //
8 // - Redistributions of source code must retain the above copyright notice, 8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer. 9 // this list of conditions and the following disclaimer.
10 // 10 //
(...skipping 4066 matching lines...) Expand 10 before | Expand all | Expand 10 after
4077 4077
4078 void Assembler::vcvt_u32_f32(QwNeonRegister dst, QwNeonRegister src) { 4078 void Assembler::vcvt_u32_f32(QwNeonRegister dst, QwNeonRegister src) {
4079 DCHECK(IsEnabled(NEON)); 4079 DCHECK(IsEnabled(NEON));
4080 DCHECK(VfpRegisterIsAvailable(dst)); 4080 DCHECK(VfpRegisterIsAvailable(dst));
4081 DCHECK(VfpRegisterIsAvailable(src)); 4081 DCHECK(VfpRegisterIsAvailable(src));
4082 emit(EncodeNeonVCVT(U32, dst, F32, src)); 4082 emit(EncodeNeonVCVT(U32, dst, F32, src));
4083 } 4083 }
4084 4084
4085 enum NeonRegType { NEON_D, NEON_Q }; 4085 enum NeonRegType { NEON_D, NEON_Q };
4086 4086
4087 void NeonSplitCode(NeonRegType type, int code, int* vm, int* m, int* encoding) {
4088 if (type == NEON_D) {
4089 DwVfpRegister::split_code(code, vm, m);
4090 } else {
4091 DCHECK_EQ(type, NEON_Q);
4092 QwNeonRegister::split_code(code, vm, m);
4093 *encoding |= B6;
4094 }
4095 }
4096
4087 enum UnaryOp { VMVN, VSWP, VABS, VABSF, VNEG, VNEGF }; 4097 enum UnaryOp { VMVN, VSWP, VABS, VABSF, VNEG, VNEGF };
4088 4098
4089 static Instr EncodeNeonUnaryOp(UnaryOp op, NeonRegType reg_type, NeonSize size, 4099 static Instr EncodeNeonUnaryOp(UnaryOp op, NeonRegType reg_type, NeonSize size,
4090 int dst_code, int src_code) { 4100 int dst_code, int src_code) {
4091 int op_encoding = 0; 4101 int op_encoding = 0;
4092 switch (op) { 4102 switch (op) {
4093 case VMVN: 4103 case VMVN:
4094 DCHECK_EQ(Neon8, size); // size == 0 for vmvn 4104 DCHECK_EQ(Neon8, size); // size == 0 for vmvn
4095 op_encoding = B10 | 0x3 * B7; 4105 op_encoding = B10 | 0x3 * B7;
4096 break; 4106 break;
(...skipping 12 matching lines...) Expand all
4109 op_encoding = B16 | 0x7 * B7; 4119 op_encoding = B16 | 0x7 * B7;
4110 break; 4120 break;
4111 case VNEGF: 4121 case VNEGF:
4112 DCHECK_EQ(Neon32, size); 4122 DCHECK_EQ(Neon32, size);
4113 op_encoding = B16 | B10 | 0x7 * B7; 4123 op_encoding = B16 | B10 | 0x7 * B7;
4114 break; 4124 break;
4115 default: 4125 default:
4116 UNREACHABLE(); 4126 UNREACHABLE();
4117 break; 4127 break;
4118 } 4128 }
4119 int vd, d, vm, m; 4129 int vd, d;
4120 if (reg_type == NEON_Q) { 4130 NeonSplitCode(reg_type, dst_code, &vd, &d, &op_encoding);
4121 op_encoding |= B6; 4131 int vm, m;
4122 QwNeonRegister::split_code(dst_code, &vd, &d); 4132 NeonSplitCode(reg_type, src_code, &vm, &m, &op_encoding);
4123 QwNeonRegister::split_code(src_code, &vm, &m); 4133
4124 } else {
4125 DCHECK_EQ(reg_type, NEON_D);
4126 DwVfpRegister::split_code(dst_code, &vd, &d);
4127 DwVfpRegister::split_code(src_code, &vm, &m);
4128 }
4129 return 0x1E7U * B23 | d * B22 | 0x3 * B20 | size * B18 | vd * B12 | m * B5 | 4134 return 0x1E7U * B23 | d * B22 | 0x3 * B20 | size * B18 | vd * B12 | m * B5 |
4130 vm | op_encoding; 4135 vm | op_encoding;
4131 } 4136 }
4132 4137
4133 void Assembler::vmvn(QwNeonRegister dst, QwNeonRegister src) { 4138 void Assembler::vmvn(QwNeonRegister dst, QwNeonRegister src) {
4134 // Qd = vmvn(Qn, Qm) SIMD bitwise negate. 4139 // Qd = vmvn(Qn, Qm) SIMD bitwise negate.
4135 // Instruction details available in ARM DDI 0406C.b, A8-966. 4140 // Instruction details available in ARM DDI 0406C.b, A8-966.
4136 DCHECK(IsEnabled(NEON)); 4141 DCHECK(IsEnabled(NEON));
4137 emit(EncodeNeonUnaryOp(VMVN, NEON_Q, Neon8, dst.code(), src.code())); 4142 emit(EncodeNeonUnaryOp(VMVN, NEON_Q, Neon8, dst.code(), src.code()));
4138 } 4143 }
(...skipping 69 matching lines...) Expand 10 before | Expand all | Expand 10 after
4208 case VORN: 4213 case VORN:
4209 op_encoding = 0x3 * B20; 4214 op_encoding = 0x3 * B20;
4210 break; 4215 break;
4211 case VAND: 4216 case VAND:
4212 // op_encoding is 0. 4217 // op_encoding is 0.
4213 break; 4218 break;
4214 default: 4219 default:
4215 UNREACHABLE(); 4220 UNREACHABLE();
4216 break; 4221 break;
4217 } 4222 }
4218 int vd, d, vn, n, vm, m; 4223 int vd, d;
4219 if (reg_type == NEON_Q) { 4224 NeonSplitCode(reg_type, dst_code, &vd, &d, &op_encoding);
4220 op_encoding |= B6; 4225 int vn, n;
4221 QwNeonRegister::split_code(dst_code, &vd, &d); 4226 NeonSplitCode(reg_type, src_code1, &vn, &n, &op_encoding);
4222 QwNeonRegister::split_code(src_code1, &vn, &n); 4227 int vm, m;
4223 QwNeonRegister::split_code(src_code2, &vm, &m); 4228 NeonSplitCode(reg_type, src_code2, &vm, &m, &op_encoding);
4224 } else { 4229
4225 DCHECK_EQ(reg_type, NEON_D);
4226 DwVfpRegister::split_code(dst_code, &vd, &d);
4227 DwVfpRegister::split_code(src_code1, &vn, &n);
4228 DwVfpRegister::split_code(src_code2, &vm, &m);
4229 }
4230 return 0x1E4U * B23 | op_encoding | d * B22 | vn * B16 | vd * B12 | B8 | 4230 return 0x1E4U * B23 | op_encoding | d * B22 | vn * B16 | vd * B12 | B8 |
4231 n * B7 | m * B5 | B4 | vm; 4231 n * B7 | m * B5 | B4 | vm;
4232 } 4232 }
4233 4233
4234 void Assembler::vand(QwNeonRegister dst, QwNeonRegister src1, 4234 void Assembler::vand(QwNeonRegister dst, QwNeonRegister src1,
4235 QwNeonRegister src2) { 4235 QwNeonRegister src2) {
4236 // Qd = vand(Qn, Qm) SIMD AND. 4236 // Qd = vand(Qn, Qm) SIMD AND.
4237 // Instruction details available in ARM DDI 0406C.b, A8.8.836. 4237 // Instruction details available in ARM DDI 0406C.b, A8.8.836.
4238 DCHECK(IsEnabled(NEON)); 4238 DCHECK(IsEnabled(NEON));
4239 emit(EncodeNeonBinaryBitwiseOp(VAND, NEON_Q, dst.code(), src1.code(), 4239 emit(EncodeNeonBinaryBitwiseOp(VAND, NEON_Q, dst.code(), src1.code(),
(...skipping 463 matching lines...) Expand 10 before | Expand all | Expand 10 after
4703 src1.split_code(&vn, &n); 4703 src1.split_code(&vn, &n);
4704 int vm, m; 4704 int vm, m;
4705 src2.split_code(&vm, &m); 4705 src2.split_code(&vm, &m);
4706 DCHECK_GT(16, bytes); 4706 DCHECK_GT(16, bytes);
4707 emit(0x1E5U * B23 | d * B22 | 0x3 * B20 | vn * B16 | vd * B12 | bytes * B8 | 4707 emit(0x1E5U * B23 | d * B22 | 0x3 * B20 | vn * B16 | vd * B12 | bytes * B8 |
4708 n * B7 | B6 | m * B5 | vm); 4708 n * B7 | B6 | m * B5 | vm);
4709 } 4709 }
4710 4710
4711 enum NeonSizedOp { VZIP, VUZP, VREV16, VREV32, VREV64, VTRN }; 4711 enum NeonSizedOp { VZIP, VUZP, VREV16, VREV32, VREV64, VTRN };
4712 4712
4713 static Instr EncodeNeonSizedOp(NeonSizedOp op, NeonSize size, 4713 static Instr EncodeNeonSizedOp(NeonSizedOp op, NeonRegType reg_type,
4714 QwNeonRegister dst, QwNeonRegister src) { 4714 NeonSize size, int dst_code, int src_code) {
4715 int op_encoding = 0; 4715 int op_encoding = 0;
4716 switch (op) { 4716 switch (op) {
4717 case VZIP: 4717 case VZIP:
4718 op_encoding = 0x2 * B16 | 0x3 * B7; 4718 op_encoding = 0x2 * B16 | 0x3 * B7;
4719 break; 4719 break;
4720 case VUZP: 4720 case VUZP:
4721 op_encoding = 0x2 * B16 | 0x2 * B7; 4721 op_encoding = 0x2 * B16 | 0x2 * B7;
4722 break; 4722 break;
4723 case VREV16: 4723 case VREV16:
4724 op_encoding = 0x2 * B7; 4724 op_encoding = 0x2 * B7;
4725 break; 4725 break;
4726 case VREV32: 4726 case VREV32:
4727 op_encoding = 0x1 * B7; 4727 op_encoding = 0x1 * B7;
4728 break; 4728 break;
4729 case VREV64: 4729 case VREV64:
4730 // op_encoding is 0; 4730 // op_encoding is 0;
4731 break; 4731 break;
4732 case VTRN: 4732 case VTRN:
4733 op_encoding = 0x2 * B16 | B7; 4733 op_encoding = 0x2 * B16 | B7;
4734 break; 4734 break;
4735 default: 4735 default:
4736 UNREACHABLE(); 4736 UNREACHABLE();
4737 break; 4737 break;
4738 } 4738 }
4739 int vd, d; 4739 int vd, d;
4740 dst.split_code(&vd, &d); 4740 NeonSplitCode(reg_type, dst_code, &vd, &d, &op_encoding);
4741 int vm, m; 4741 int vm, m;
4742 src.split_code(&vm, &m); 4742 NeonSplitCode(reg_type, src_code, &vm, &m, &op_encoding);
4743
4743 int sz = static_cast<int>(size); 4744 int sz = static_cast<int>(size);
4744 return 0x1E7U * B23 | d * B22 | 0x3 * B20 | sz * B18 | vd * B12 | B6 | 4745 return 0x1E7U * B23 | d * B22 | 0x3 * B20 | sz * B18 | vd * B12 | m * B5 |
4745 m * B5 | vm | op_encoding; 4746 vm | op_encoding;
4747 }
4748
4749 void Assembler::vzip(NeonSize size, DwVfpRegister src1, DwVfpRegister src2) {
4750 DCHECK(IsEnabled(NEON));
4751 // vzip.<size>(Dn, Dm) SIMD zip (interleave).
4752 // Instruction details available in ARM DDI 0406C.b, A8-1102.
4753 emit(EncodeNeonSizedOp(VZIP, NEON_D, size, src1.code(), src2.code()));
4746 } 4754 }
4747 4755
4748 void Assembler::vzip(NeonSize size, QwNeonRegister src1, QwNeonRegister src2) { 4756 void Assembler::vzip(NeonSize size, QwNeonRegister src1, QwNeonRegister src2) {
4749 DCHECK(IsEnabled(NEON)); 4757 DCHECK(IsEnabled(NEON));
4750 // Qd = vzip.<size>(Qn, Qm) SIMD zip (interleave). 4758 // vzip.<size>(Qn, Qm) SIMD zip (interleave).
4751 // Instruction details available in ARM DDI 0406C.b, A8-1102. 4759 // Instruction details available in ARM DDI 0406C.b, A8-1102.
4752 emit(EncodeNeonSizedOp(VZIP, size, src1, src2)); 4760 emit(EncodeNeonSizedOp(VZIP, NEON_Q, size, src1.code(), src2.code()));
4761 }
4762
4763 void Assembler::vuzp(NeonSize size, DwVfpRegister src1, DwVfpRegister src2) {
4764 DCHECK(IsEnabled(NEON));
4765 // vuzp.<size>(Dn, Dm) SIMD un-zip (de-interleave).
4766 // Instruction details available in ARM DDI 0406C.b, A8-1100.
4767 emit(EncodeNeonSizedOp(VUZP, NEON_D, size, src1.code(), src2.code()));
4753 } 4768 }
4754 4769
4755 void Assembler::vuzp(NeonSize size, QwNeonRegister src1, QwNeonRegister src2) { 4770 void Assembler::vuzp(NeonSize size, QwNeonRegister src1, QwNeonRegister src2) {
4756 DCHECK(IsEnabled(NEON)); 4771 DCHECK(IsEnabled(NEON));
4757 // Qd = vuzp.<size>(Qn, Qm) SIMD un-zip (de-interleave). 4772 // vuzp.<size>(Qn, Qm) SIMD un-zip (de-interleave).
4758 // Instruction details available in ARM DDI 0406C.b, A8-1100. 4773 // Instruction details available in ARM DDI 0406C.b, A8-1100.
4759 emit(EncodeNeonSizedOp(VUZP, size, src1, src2)); 4774 emit(EncodeNeonSizedOp(VUZP, NEON_Q, size, src1.code(), src2.code()));
4760 } 4775 }
4761 4776
4762 void Assembler::vrev16(NeonSize size, QwNeonRegister dst, QwNeonRegister src) { 4777 void Assembler::vrev16(NeonSize size, QwNeonRegister dst, QwNeonRegister src) {
4763 DCHECK(IsEnabled(NEON)); 4778 DCHECK(IsEnabled(NEON));
4764 // Qd = vrev<op_size>.<size>(Qn, Qm) SIMD scalar reverse. 4779 // Qd = vrev16.<size>(Qm) SIMD element reverse.
4765 // Instruction details available in ARM DDI 0406C.b, A8-1028. 4780 // Instruction details available in ARM DDI 0406C.b, A8-1028.
4766 emit(EncodeNeonSizedOp(VREV16, size, dst, src)); 4781 emit(EncodeNeonSizedOp(VREV16, NEON_Q, size, dst.code(), src.code()));
4767 } 4782 }
4768 4783
4769 void Assembler::vrev32(NeonSize size, QwNeonRegister dst, QwNeonRegister src) { 4784 void Assembler::vrev32(NeonSize size, QwNeonRegister dst, QwNeonRegister src) {
4770 DCHECK(IsEnabled(NEON)); 4785 DCHECK(IsEnabled(NEON));
4771 // Qd = vrev<op_size>.<size>(Qn, Qm) SIMD scalar reverse. 4786 // Qd = vrev32.<size>(Qm) SIMD element reverse.
4772 // Instruction details available in ARM DDI 0406C.b, A8-1028. 4787 // Instruction details available in ARM DDI 0406C.b, A8-1028.
4773 emit(EncodeNeonSizedOp(VREV32, size, dst, src)); 4788 emit(EncodeNeonSizedOp(VREV32, NEON_Q, size, dst.code(), src.code()));
4774 } 4789 }
4775 4790
4776 void Assembler::vrev64(NeonSize size, QwNeonRegister dst, QwNeonRegister src) { 4791 void Assembler::vrev64(NeonSize size, QwNeonRegister dst, QwNeonRegister src) {
4777 DCHECK(IsEnabled(NEON)); 4792 DCHECK(IsEnabled(NEON));
4778 // Qd = vrev<op_size>.<size>(Qn, Qm) SIMD scalar reverse. 4793 // Qd = vrev64.<size>(Qm) SIMD element reverse.
4779 // Instruction details available in ARM DDI 0406C.b, A8-1028. 4794 // Instruction details available in ARM DDI 0406C.b, A8-1028.
4780 emit(EncodeNeonSizedOp(VREV64, size, dst, src)); 4795 emit(EncodeNeonSizedOp(VREV64, NEON_Q, size, dst.code(), src.code()));
4796 }
4797
4798 void Assembler::vtrn(NeonSize size, DwVfpRegister src1, DwVfpRegister src2) {
4799 DCHECK(IsEnabled(NEON));
4800 // vtrn.<size>(Dn, Dm) SIMD element transpose.
4801 // Instruction details available in ARM DDI 0406C.b, A8-1096.
4802 emit(EncodeNeonSizedOp(VTRN, NEON_D, size, src1.code(), src2.code()));
4781 } 4803 }
4782 4804
4783 void Assembler::vtrn(NeonSize size, QwNeonRegister src1, QwNeonRegister src2) { 4805 void Assembler::vtrn(NeonSize size, QwNeonRegister src1, QwNeonRegister src2) {
4784 DCHECK(IsEnabled(NEON)); 4806 DCHECK(IsEnabled(NEON));
4785 // Qd = vrev<op_size>.<size>(Qn, Qm) SIMD scalar reverse. 4807 // vtrn.<size>(Qn, Qm) SIMD element transpose.
4786 // Instruction details available in ARM DDI 0406C.b, A8-1096. 4808 // Instruction details available in ARM DDI 0406C.b, A8-1096.
4787 emit(EncodeNeonSizedOp(VTRN, size, src1, src2)); 4809 emit(EncodeNeonSizedOp(VTRN, NEON_Q, size, src1.code(), src2.code()));
4788 } 4810 }
4789 4811
4790 // Encode NEON vtbl / vtbx instruction. 4812 // Encode NEON vtbl / vtbx instruction.
4791 static Instr EncodeNeonVTB(DwVfpRegister dst, const NeonListOperand& list, 4813 static Instr EncodeNeonVTB(DwVfpRegister dst, const NeonListOperand& list,
4792 DwVfpRegister index, bool vtbx) { 4814 DwVfpRegister index, bool vtbx) {
4793 // Dd = vtbl(table, Dm) SIMD vector permute, zero at out of range indices. 4815 // Dd = vtbl(table, Dm) SIMD vector permute, zero at out of range indices.
4794 // Instruction details available in ARM DDI 0406C.b, A8-1094. 4816 // Instruction details available in ARM DDI 0406C.b, A8-1094.
4795 // Dd = vtbx(table, Dm) SIMD vector permute, skip out of range indices. 4817 // Dd = vtbx(table, Dm) SIMD vector permute, skip out of range indices.
4796 // Instruction details available in ARM DDI 0406C.b, A8-1094. 4818 // Instruction details available in ARM DDI 0406C.b, A8-1094.
4797 int vd, d; 4819 int vd, d;
(...skipping 589 matching lines...) Expand 10 before | Expand all | Expand 10 after
5387 } 5409 }
5388 5410
5389 void PatchingAssembler::FlushICache(Isolate* isolate) { 5411 void PatchingAssembler::FlushICache(Isolate* isolate) {
5390 Assembler::FlushICache(isolate, buffer_, buffer_size_ - kGap); 5412 Assembler::FlushICache(isolate, buffer_, buffer_size_ - kGap);
5391 } 5413 }
5392 5414
5393 } // namespace internal 5415 } // namespace internal
5394 } // namespace v8 5416 } // namespace v8
5395 5417
5396 #endif // V8_TARGET_ARCH_ARM 5418 #endif // V8_TARGET_ARCH_ARM
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