[ARM] Implement D-register versions of vzip, vuzp, and vtrn.

src/arm/assembler-arm.cc

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
 // are met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 4066 matching lines @@
 
 void Assembler::vcvt_u32_f32(QwNeonRegister dst, QwNeonRegister src) {
   DCHECK(IsEnabled(NEON));
   DCHECK(VfpRegisterIsAvailable(dst));
   DCHECK(VfpRegisterIsAvailable(src));
   emit(EncodeNeonVCVT(U32, dst, F32, src));
 }
 
 enum NeonRegType { NEON_D, NEON_Q };
 
+void NeonSplitCode(NeonRegType type, int code, int* vm, int* m, int* encoding) {
+  if (type == NEON_D) {
+    DwVfpRegister::split_code(code, vm, m);
+  } else {
+    DCHECK_EQ(type, NEON_Q);
+    QwNeonRegister::split_code(code, vm, m);
+    *encoding |= B6;
+  }
+}
+
 enum UnaryOp { VMVN, VSWP, VABS, VABSF, VNEG, VNEGF };
 
 static Instr EncodeNeonUnaryOp(UnaryOp op, NeonRegType reg_type, NeonSize size,
                                int dst_code, int src_code) {
   int op_encoding = 0;
   switch (op) {
     case VMVN:
       DCHECK_EQ(Neon8, size);  // size == 0 for vmvn
       op_encoding = B10 | 0x3 * B7;
       break;
@@ skipping 12 matching lines @@
       op_encoding = B16 | 0x7 * B7;
       break;
     case VNEGF:
       DCHECK_EQ(Neon32, size);
       op_encoding = B16 | B10 | 0x7 * B7;
       break;
     default:
       UNREACHABLE();
       break;
   }
-  int vd, d, vm, m;
-  if (reg_type == NEON_Q) {
-    op_encoding |= B6;
-    QwNeonRegister::split_code(dst_code, &vd, &d);
-    QwNeonRegister::split_code(src_code, &vm, &m);
-  } else {
-    DCHECK_EQ(reg_type, NEON_D);
-    DwVfpRegister::split_code(dst_code, &vd, &d);
-    DwVfpRegister::split_code(src_code, &vm, &m);
-  }
+  int vd, d;
+  NeonSplitCode(reg_type, dst_code, &vd, &d, &op_encoding);
+  int vm, m;
+  NeonSplitCode(reg_type, src_code, &vm, &m, &op_encoding);
+
   return 0x1E7U * B23 | d * B22 | 0x3 * B20 | size * B18 | vd * B12 | m * B5 |
          vm | op_encoding;
 }
 
 void Assembler::vmvn(QwNeonRegister dst, QwNeonRegister src) {
   // Qd = vmvn(Qn, Qm) SIMD bitwise negate.
   // Instruction details available in ARM DDI 0406C.b, A8-966.
   DCHECK(IsEnabled(NEON));
   emit(EncodeNeonUnaryOp(VMVN, NEON_Q, Neon8, dst.code(), src.code()));
 }
@@ skipping 69 matching lines @@
     case VORN:
       op_encoding = 0x3 * B20;
       break;
     case VAND:
       // op_encoding is 0.
       break;
     default:
       UNREACHABLE();
       break;
   }
-  int vd, d, vn, n, vm, m;
-  if (reg_type == NEON_Q) {
-    op_encoding |= B6;
-    QwNeonRegister::split_code(dst_code, &vd, &d);
-    QwNeonRegister::split_code(src_code1, &vn, &n);
-    QwNeonRegister::split_code(src_code2, &vm, &m);
-  } else {
-    DCHECK_EQ(reg_type, NEON_D);
-    DwVfpRegister::split_code(dst_code, &vd, &d);
-    DwVfpRegister::split_code(src_code1, &vn, &n);
-    DwVfpRegister::split_code(src_code2, &vm, &m);
-  }
+  int vd, d;
+  NeonSplitCode(reg_type, dst_code, &vd, &d, &op_encoding);
+  int vn, n;
+  NeonSplitCode(reg_type, src_code1, &vn, &n, &op_encoding);
+  int vm, m;
+  NeonSplitCode(reg_type, src_code2, &vm, &m, &op_encoding);
+
   return 0x1E4U * B23 | op_encoding | d * B22 | vn * B16 | vd * B12 | B8 |
          n * B7 | m * B5 | B4 | vm;
 }
 
 void Assembler::vand(QwNeonRegister dst, QwNeonRegister src1,
                      QwNeonRegister src2) {
   // Qd = vand(Qn, Qm) SIMD AND.
   // Instruction details available in ARM DDI 0406C.b, A8.8.836.
   DCHECK(IsEnabled(NEON));
   emit(EncodeNeonBinaryBitwiseOp(VAND, NEON_Q, dst.code(), src1.code(),
@@ skipping 463 matching lines @@
   src1.split_code(&vn, &n);
   int vm, m;
   src2.split_code(&vm, &m);
   DCHECK_GT(16, bytes);
   emit(0x1E5U * B23 | d * B22 | 0x3 * B20 | vn * B16 | vd * B12 | bytes * B8 |
        n * B7 | B6 | m * B5 | vm);
 }
 
 enum NeonSizedOp { VZIP, VUZP, VREV16, VREV32, VREV64, VTRN };
 
-static Instr EncodeNeonSizedOp(NeonSizedOp op, NeonSize size,
-                               QwNeonRegister dst, QwNeonRegister src) {
+static Instr EncodeNeonSizedOp(NeonSizedOp op, NeonRegType reg_type,
+                               NeonSize size, int dst_code, int src_code) {
   int op_encoding = 0;
   switch (op) {
     case VZIP:
       op_encoding = 0x2 * B16 | 0x3 * B7;
       break;
     case VUZP:
       op_encoding = 0x2 * B16 | 0x2 * B7;
       break;
     case VREV16:
       op_encoding = 0x2 * B7;
       break;
     case VREV32:
       op_encoding = 0x1 * B7;
       break;
     case VREV64:
       // op_encoding is 0;
       break;
     case VTRN:
       op_encoding = 0x2 * B16 | B7;
       break;
     default:
       UNREACHABLE();
       break;
   }
   int vd, d;
-  dst.split_code(&vd, &d);
+  NeonSplitCode(reg_type, dst_code, &vd, &d, &op_encoding);
   int vm, m;
-  src.split_code(&vm, &m);
+  NeonSplitCode(reg_type, src_code, &vm, &m, &op_encoding);
+
   int sz = static_cast<int>(size);
-  return 0x1E7U * B23 | d * B22 | 0x3 * B20 | sz * B18 | vd * B12 | B6 |
-         m * B5 | vm | op_encoding;
+  return 0x1E7U * B23 | d * B22 | 0x3 * B20 | sz * B18 | vd * B12 | m * B5 |
+         vm | op_encoding;
+}
+
+void Assembler::vzip(NeonSize size, DwVfpRegister src1, DwVfpRegister src2) {
+  DCHECK(IsEnabled(NEON));
+  // vzip.<size>(Dn, Dm) SIMD zip (interleave).
+  // Instruction details available in ARM DDI 0406C.b, A8-1102.
+  emit(EncodeNeonSizedOp(VZIP, NEON_D, size, src1.code(), src2.code()));
 }
 
 void Assembler::vzip(NeonSize size, QwNeonRegister src1, QwNeonRegister src2) {
   DCHECK(IsEnabled(NEON));
-  // Qd = vzip.<size>(Qn, Qm) SIMD zip (interleave).
+  // vzip.<size>(Qn, Qm) SIMD zip (interleave).
   // Instruction details available in ARM DDI 0406C.b, A8-1102.
-  emit(EncodeNeonSizedOp(VZIP, size, src1, src2));
+  emit(EncodeNeonSizedOp(VZIP, NEON_Q, size, src1.code(), src2.code()));
+}
+
+void Assembler::vuzp(NeonSize size, DwVfpRegister src1, DwVfpRegister src2) {
+  DCHECK(IsEnabled(NEON));
+  // vuzp.<size>(Dn, Dm) SIMD un-zip (de-interleave).
+  // Instruction details available in ARM DDI 0406C.b, A8-1100.
+  emit(EncodeNeonSizedOp(VUZP, NEON_D, size, src1.code(), src2.code()));
 }
 
 void Assembler::vuzp(NeonSize size, QwNeonRegister src1, QwNeonRegister src2) {
   DCHECK(IsEnabled(NEON));
-  // Qd = vuzp.<size>(Qn, Qm) SIMD un-zip (de-interleave).
+  // vuzp.<size>(Qn, Qm) SIMD un-zip (de-interleave).
   // Instruction details available in ARM DDI 0406C.b, A8-1100.
-  emit(EncodeNeonSizedOp(VUZP, size, src1, src2));
+  emit(EncodeNeonSizedOp(VUZP, NEON_Q, size, src1.code(), src2.code()));
 }
 
 void Assembler::vrev16(NeonSize size, QwNeonRegister dst, QwNeonRegister src) {
   DCHECK(IsEnabled(NEON));
-  // Qd = vrev<op_size>.<size>(Qn, Qm) SIMD scalar reverse.
+  // Qd = vrev16.<size>(Qm) SIMD element reverse.
   // Instruction details available in ARM DDI 0406C.b, A8-1028.
-  emit(EncodeNeonSizedOp(VREV16, size, dst, src));
+  emit(EncodeNeonSizedOp(VREV16, NEON_Q, size, dst.code(), src.code()));
 }
 
 void Assembler::vrev32(NeonSize size, QwNeonRegister dst, QwNeonRegister src) {
   DCHECK(IsEnabled(NEON));
-  // Qd = vrev<op_size>.<size>(Qn, Qm) SIMD scalar reverse.
+  // Qd = vrev32.<size>(Qm) SIMD element reverse.
   // Instruction details available in ARM DDI 0406C.b, A8-1028.
-  emit(EncodeNeonSizedOp(VREV32, size, dst, src));
+  emit(EncodeNeonSizedOp(VREV32, NEON_Q, size, dst.code(), src.code()));
 }
 
 void Assembler::vrev64(NeonSize size, QwNeonRegister dst, QwNeonRegister src) {
   DCHECK(IsEnabled(NEON));
-  // Qd = vrev<op_size>.<size>(Qn, Qm) SIMD scalar reverse.
+  // Qd = vrev64.<size>(Qm) SIMD element reverse.
   // Instruction details available in ARM DDI 0406C.b, A8-1028.
-  emit(EncodeNeonSizedOp(VREV64, size, dst, src));
+  emit(EncodeNeonSizedOp(VREV64, NEON_Q, size, dst.code(), src.code()));
+}
+
+void Assembler::vtrn(NeonSize size, DwVfpRegister src1, DwVfpRegister src2) {
+  DCHECK(IsEnabled(NEON));
+  // vtrn.<size>(Dn, Dm) SIMD element transpose.
+  // Instruction details available in ARM DDI 0406C.b, A8-1096.
+  emit(EncodeNeonSizedOp(VTRN, NEON_D, size, src1.code(), src2.code()));
 }
 
 void Assembler::vtrn(NeonSize size, QwNeonRegister src1, QwNeonRegister src2) {
   DCHECK(IsEnabled(NEON));
-  // Qd = vrev<op_size>.<size>(Qn, Qm) SIMD scalar reverse.
+  // vtrn.<size>(Qn, Qm) SIMD element transpose.
   // Instruction details available in ARM DDI 0406C.b, A8-1096.
-  emit(EncodeNeonSizedOp(VTRN, size, src1, src2));
+  emit(EncodeNeonSizedOp(VTRN, NEON_Q, size, src1.code(), src2.code()));
 }
 
 // Encode NEON vtbl / vtbx instruction.
 static Instr EncodeNeonVTB(DwVfpRegister dst, const NeonListOperand& list,
                            DwVfpRegister index, bool vtbx) {
   // Dd = vtbl(table, Dm) SIMD vector permute, zero at out of range indices.
   // Instruction details available in ARM DDI 0406C.b, A8-1094.
   // Dd = vtbx(table, Dm) SIMD vector permute, skip out of range indices.
   // Instruction details available in ARM DDI 0406C.b, A8-1094.
   int vd, d;
@@ skipping 589 matching lines @@
 }
 
 void PatchingAssembler::FlushICache(Isolate* isolate) {
   Assembler::FlushICache(isolate, buffer_, buffer_size_ - kGap);
 }
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_TARGET_ARCH_ARM