[turbofan] introduce Int32/64AbsWithOverflow optional operator

src/s390/disasm-s390.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 // A Disassembler object is used to disassemble a block of code instruction by
 // instruction. The default implementation of the NameConverter object can be
 // overriden to modify register names or to do symbol lookup on addresses.
 //
 // The example below will disassemble a block of code and print it to stdout.
 //
@@ skipping 1049 matching lines @@
     case FIDBRA:
       Format(instr, "fidbra\t'f5,'m2,'f6,'m3");
       break;
     // TRAP4 is used in calling to native function. it will not be generated
     // in native code.
     case TRAP4: {
       Format(instr, "trap4");
       break;
     }
     case LPGR:
-      Format(instr, "lpgr\t'r1, 'r2");
+      Format(instr, "lpgr\t'r5,'r6");
       break;
     case LPGFR:
-      Format(instr, "lpgfr\t'r1,'r2");
+      Format(instr, "lpgfr\t'r5,'r6");
       break;
     default:
       return false;
   }
   return true;
 }
 
 // Disassembles Six Byte S390 Instructions
 // @return true if successfully decoded
 bool Decoder::DecodeSixByte(Instruction* instr) {
@@ skipping 480 matching lines @@
     byte* prev_pc = pc;
     pc += d.InstructionDecode(buffer, pc);
     v8::internal::PrintF(f, "%p    %08x      %s\n", static_cast<void*>(prev_pc),
                          *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
   }
 }
 
 }  // namespace disasm
 
 #endif  // V8_TARGET_ARCH_S390