Require CMOV support for the ia32 port.

src/ia32/assembler-ia32.cc

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
 // are met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 81 matching lines @@
   CPU cpu;
   if (cpu.has_sse41()) {
     probed_features |= static_cast<uint64_t>(1) << SSE4_1;
   }
   if (cpu.has_sse3()) {
     probed_features |= static_cast<uint64_t>(1) << SSE3;
   }
 
   CHECK(cpu.has_sse2());  // SSE2 support is mandatory.
 
-  if (cpu.has_cmov()) {
-    probed_features |= static_cast<uint64_t>(1) << CMOV;
-  }
+  CHECK(cpu.has_cmov());  // CMOV support is mandatory.
 
   // SAHF must be available in compat/legacy mode.
   ASSERT(cpu.has_sahf());
   probed_features |= static_cast<uint64_t>(1) << SAHF;
 
   uint64_t platform_features = OS::CpuFeaturesImpliedByPlatform();
   supported_ = probed_features | platform_features;
   found_by_runtime_probing_only_ = probed_features & ~platform_features;
 }
 
@@ skipping 514 matching lines @@
 
 void Assembler::movzx_w(Register dst, const Operand& src) {
   EnsureSpace ensure_space(this);
   EMIT(0x0F);
   EMIT(0xB7);
   emit_operand(dst, src);
 }
 
 
 void Assembler::cmov(Condition cc, Register dst, const Operand& src) {
-  ASSERT(IsEnabled(CMOV));
   EnsureSpace ensure_space(this);
   // Opcode: 0f 40 + cc /r.
   EMIT(0x0F);
   EMIT(0x40 + cc);
   emit_operand(dst, src);
 }
 
 
 void Assembler::cld() {
   EnsureSpace ensure_space(this);
@@ skipping 2027 matching lines @@
     fprintf(coverage_log, "%s\n", file_line);
     fflush(coverage_log);
   }
 }
 
 #endif
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_IA32