Presubmit checks recover.

src/mips/simulator-mips.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <limits.h>
 #include <stdarg.h>
 #include <stdlib.h>
 #include <cmath>
 
 #include "v8.h"
@@ skipping 822 matching lines @@
   intptr_t address = reinterpret_cast<intptr_t>(instr);
   void* page = reinterpret_cast<void*>(address & (~CachePage::kPageMask));
   void* line = reinterpret_cast<void*>(address & (~CachePage::kLineMask));
   int offset = (address & CachePage::kPageMask);
   CachePage* cache_page = GetCachePage(i_cache, page);
   char* cache_valid_byte = cache_page->ValidityByte(offset);
   bool cache_hit = (*cache_valid_byte == CachePage::LINE_VALID);
   char* cached_line = cache_page->CachedData(offset & ~CachePage::kLineMask);
   if (cache_hit) {
     // Check that the data in memory matches the contents of the I-cache.
-    CHECK(memcmp(reinterpret_cast<void*>(instr),
-                 cache_page->CachedData(offset),
-                 Instruction::kInstrSize) == 0);
+    CHECK_EQ(0, memcmp(reinterpret_cast<void*>(instr),
+                       cache_page->CachedData(offset),
+                       Instruction::kInstrSize));
   } else {
     // Cache miss.  Load memory into the cache.
     OS::MemCopy(cached_line, line, CachePage::kLineLength);
     *cache_valid_byte = CachePage::LINE_VALID;
   }
 }
 
 
 void Simulator::Initialize(Isolate* isolate) {
   if (isolate->simulator_initialized()) return;
@@ skipping 899 matching lines @@
           break;
         case S:
         case D:
         case W:
         case L:
         case PS:
           // Do everything in the execution step.
           break;
         default:
           UNIMPLEMENTED_MIPS();
-      };
+      }
       break;
     case COP1X:
       break;
     case SPECIAL:
       switch (instr->FunctionFieldRaw()) {
         case JR:
         case JALR:
           next_pc = get_register(instr->RsValue());
           return_addr_reg = instr->RdValue();
           break;
@@ skipping 116 matching lines @@
         case MOVZ:
         case MOVCI:
           // No action taken on decode.
           break;
         case DIV:
         case DIVU:
           // div and divu never raise exceptions.
           break;
         default:
           UNREACHABLE();
-      };
+      }
       break;
     case SPECIAL2:
       switch (instr->FunctionFieldRaw()) {
         case MUL:
           alu_out = rs_u * rt_u;  // Only the lower 32 bits are kept.
           break;
         case CLZ:
           // MIPS32 spec: If no bits were set in GPR rs, the result written to
           // GPR rd is 32.
           // GCC __builtin_clz: If input is 0, the result is undefined.
           alu_out =
               rs_u == 0 ? 32 : CompilerIntrinsics::CountLeadingZeros(rs_u);
           break;
         default:
           UNREACHABLE();
-      };
+      }
       break;
     case SPECIAL3:
       switch (instr->FunctionFieldRaw()) {
         case INS: {   // Mips32r2 instruction.
           // Interpret rd field as 5-bit msb of insert.
           uint16_t msb = rd_reg;
           // Interpret sa field as 5-bit lsb of insert.
           uint16_t lsb = sa;
           uint16_t size = msb - lsb + 1;
           uint32_t mask = (1 << size) - 1;
           alu_out = (rt_u & ~(mask << lsb)) | ((rs_u & mask) << lsb);
           break;
         }
         case EXT: {   // Mips32r2 instruction.
           // Interpret rd field as 5-bit msb of extract.
           uint16_t msb = rd_reg;
           // Interpret sa field as 5-bit lsb of extract.
           uint16_t lsb = sa;
           uint16_t size = msb + 1;
           uint32_t mask = (1 << size) - 1;
           alu_out = (rs_u & (mask << lsb)) >> lsb;
           break;
         }
         default:
           UNREACHABLE();
-      };
+      }
       break;
     default:
       UNREACHABLE();
-  };
+  }
 }
 
 
 void Simulator::DecodeTypeRegister(Instruction* instr) {
   // Instruction fields.
   const Opcode   op     = instr->OpcodeFieldRaw();
   const int32_t  rs_reg = instr->RsValue();
   const int32_t  rs     = get_register(rs_reg);
   const uint32_t rs_u   = static_cast<uint32_t>(rs);
   const int32_t  rt_reg = instr->RtValue();
@@ skipping 238 matching lines @@
             case CVT_S_W:   // Convert word to float (single).
               alu_out = get_fpu_register(fs_reg);
               set_fpu_register_float(fd_reg, static_cast<float>(alu_out));
               break;
             case CVT_D_W:   // Convert word to double.
               alu_out = get_fpu_register(fs_reg);
               set_fpu_register_double(fd_reg, static_cast<double>(alu_out));
               break;
             default:
               UNREACHABLE();
-          };
+          }
           break;
         case L:
           switch (instr->FunctionFieldRaw()) {
           case CVT_D_L:  // Mips32r2 instruction.
             // Watch the signs here, we want 2 32-bit vals
             // to make a sign-64.
             i64 = static_cast<uint32_t>(get_fpu_register(fs_reg));
             i64 |= static_cast<int64_t>(get_fpu_register(fs_reg + 1)) << 32;
             set_fpu_register_double(fd_reg, static_cast<double>(i64));
             break;
             case CVT_S_L:
               UNIMPLEMENTED_MIPS();
               break;
             default:
               UNREACHABLE();
           }
           break;
         case PS:
           break;
         default:
           UNREACHABLE();
-      };
+      }
       break;
     case COP1X:
       switch (instr->FunctionFieldRaw()) {
         case MADD_D:
           double fr, ft, fs;
           fr = get_fpu_register_double(fr_reg);
           fs = get_fpu_register_double(fs_reg);
           ft = get_fpu_register_double(ft_reg);
           set_fpu_register_double(fd_reg, fs * ft + fr);
           break;
         default:
           UNREACHABLE();
-      };
+      }
       break;
     case SPECIAL:
       switch (instr->FunctionFieldRaw()) {
         case JR: {
           Instruction* branch_delay_instr = reinterpret_cast<Instruction*>(
               current_pc+Instruction::kInstrSize);
           BranchDelayInstructionDecode(branch_delay_instr);
           set_pc(next_pc);
           pc_modified_ = true;
           break;
@@ skipping 60 matching lines @@
           } else {
             if (!test_fcsr_bit(fcsr_cc)) set_register(rd_reg, rs);
           }
           break;
         }
         case MOVZ:
           if (!rt) set_register(rd_reg, rs);
           break;
         default:  // For other special opcodes we do the default operation.
           set_register(rd_reg, alu_out);
-      };
+      }
       break;
     case SPECIAL2:
       switch (instr->FunctionFieldRaw()) {
         case MUL:
           set_register(rd_reg, alu_out);
           // HI and LO are UNPREDICTABLE after the operation.
           set_register(LO, Unpredictable);
           set_register(HI, Unpredictable);
           break;
         default:  // For other special2 opcodes we do the default operation.
           set_register(rd_reg, alu_out);
       }
       break;
     case SPECIAL3:
       switch (instr->FunctionFieldRaw()) {
         case INS:
           // Ins instr leaves result in Rt, rather than Rd.
           set_register(rt_reg, alu_out);
           break;
         case EXT:
           // Ext instr leaves result in Rt, rather than Rd.
           set_register(rt_reg, alu_out);
           break;
         default:
           UNREACHABLE();
-      };
+      }
       break;
     // Unimplemented opcodes raised an error in the configuration step before,
     // so we can use the default here to set the destination register in common
     // cases.
     default:
       set_register(rd_reg, alu_out);
-  };
+  }
 }
 
 
 // Type 2: instructions using a 16 bytes immediate. (e.g. addi, beq).
 void Simulator::DecodeTypeImmediate(Instruction* instr) {
   // Instruction fields.
   Opcode   op     = instr->OpcodeFieldRaw();
   int32_t  rs     = get_register(instr->RsValue());
   uint32_t rs_u   = static_cast<uint32_t>(rs);
   int32_t  rt_reg = instr->RtValue();  // Destination register.
@@ skipping 40 matching lines @@
           execute_branch_delay_instruction = true;
           // Set next_pc.
           if (do_branch) {
             next_pc = current_pc + (imm16 << 2) + Instruction::kInstrSize;
           } else {
             next_pc = current_pc + kBranchReturnOffset;
           }
           break;
         default:
           UNREACHABLE();
-      };
+      }
       break;
     // ------------- REGIMM class.
     case REGIMM:
       switch (instr->RtFieldRaw()) {
         case BLTZ:
           do_branch = (rs  < 0);
           break;
         case BLTZAL:
           do_branch = rs  < 0;
           break;
         case BGEZ:
           do_branch = rs >= 0;
           break;
         case BGEZAL:
           do_branch = rs >= 0;
           break;
         default:
           UNREACHABLE();
-      };
+      }
       switch (instr->RtFieldRaw()) {
         case BLTZ:
         case BLTZAL:
         case BGEZ:
         case BGEZAL:
           // Branch instructions common part.
           execute_branch_delay_instruction = true;
           // Set next_pc.
           if (do_branch) {
             next_pc = current_pc + (imm16 << 2) + Instruction::kInstrSize;
             if (instr->IsLinkingInstruction()) {
               set_register(31, current_pc + kBranchReturnOffset);
             }
           } else {
             next_pc = current_pc + kBranchReturnOffset;
           }
         default:
           break;
-        };
+        }
     break;  // case REGIMM.
     // ------------- Branch instructions.
     // When comparing to zero, the encoding of rt field is always 0, so we don't
     // need to replace rt with zero.
     case BEQ:
       do_branch = (rs == rt);
       break;
     case BNE:
       do_branch = rs != rt;
       break;
@@ skipping 112 matching lines @@
     case LDC1:
       addr = rs + se_imm16;
       fp_out = ReadD(addr, instr);
       break;
     case SWC1:
     case SDC1:
       addr = rs + se_imm16;
       break;
     default:
       UNREACHABLE();
-  };
+  }
 
   // ---------- Raise exceptions triggered.
   SignalExceptions();
 
   // ---------- Execution.
   switch (op) {
     // ------------- Branch instructions.
     case BEQ:
     case BNE:
     case BLEZ:
@@ skipping 55 matching lines @@
     case SWC1:
       addr = rs + se_imm16;
       WriteW(addr, get_fpu_register(ft_reg), instr);
       break;
     case SDC1:
       addr = rs + se_imm16;
       WriteD(addr, get_fpu_register_double(ft_reg), instr);
       break;
     default:
       break;
-  };
+  }
 
 
   if (execute_branch_delay_instruction) {
     // Execute branch delay slot
     // We don't check for end_sim_pc. First it should not be met as the current
     // pc is valid. Secondly a jump should always execute its branch delay slot.
     Instruction* branch_delay_instr =
       reinterpret_cast<Instruction*>(current_pc+Instruction::kInstrSize);
     BranchDelayInstructionDecode(branch_delay_instr);
   }
@@ skipping 244 matching lines @@
 }
 
 
 #undef UNSUPPORTED
 
 } }  // namespace v8::internal
 
 #endif  // USE_SIMULATOR
 
 #endif  // V8_TARGET_ARCH_MIPS