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Side by Side Diff: src/mips/disasm-mips.cc

Issue 277913002: Presubmit checks recover. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Rebasing Created 6 years, 7 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 // A Disassembler object is used to disassemble a block of code instruction by 5 // A Disassembler object is used to disassemble a block of code instruction by
6 // instruction. The default implementation of the NameConverter object can be 6 // instruction. The default implementation of the NameConverter object can be
7 // overriden to modify register names or to do symbol lookup on addresses. 7 // overriden to modify register names or to do symbol lookup on addresses.
8 // 8 //
9 // The example below will disassemble a block of code and print it to stdout. 9 // The example below will disassemble a block of code and print it to stdout.
10 // 10 //
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270 case TLTU: 270 case TLTU:
271 case TEQ: 271 case TEQ:
272 case TNE: { 272 case TNE: {
273 int32_t code = instr->Bits(15, 6); 273 int32_t code = instr->Bits(15, 6);
274 out_buffer_pos_ += 274 out_buffer_pos_ +=
275 OS::SNPrintF(out_buffer_ + out_buffer_pos_, "0x%03x", code); 275 OS::SNPrintF(out_buffer_ + out_buffer_pos_, "0x%03x", code);
276 break; 276 break;
277 } 277 }
278 default: // Not a break or trap instruction. 278 default: // Not a break or trap instruction.
279 break; 279 break;
280 }; 280 }
281 } 281 }
282 282
283 283
284 // Printing of instruction name. 284 // Printing of instruction name.
285 void Decoder::PrintInstructionName(Instruction* instr) { 285 void Decoder::PrintInstructionName(Instruction* instr) {
286 } 286 }
287 287
288 288
289 // Handle all register based formatting in this function to reduce the 289 // Handle all register based formatting in this function to reduce the
290 // complexity of FormatOption. 290 // complexity of FormatOption.
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400 case 'b': { // 'bc - Special for bc1 cc field. 400 case 'b': { // 'bc - Special for bc1 cc field.
401 ASSERT(STRING_STARTS_WITH(format, "bc")); 401 ASSERT(STRING_STARTS_WITH(format, "bc"));
402 PrintBc(instr); 402 PrintBc(instr);
403 return 2; 403 return 2;
404 } 404 }
405 case 'C': { // 'Cc - Special for c.xx.d cc field. 405 case 'C': { // 'Cc - Special for c.xx.d cc field.
406 ASSERT(STRING_STARTS_WITH(format, "Cc")); 406 ASSERT(STRING_STARTS_WITH(format, "Cc"));
407 PrintCc(instr); 407 PrintCc(instr);
408 return 2; 408 return 2;
409 } 409 }
410 }; 410 }
411 UNREACHABLE(); 411 UNREACHABLE();
412 return -1; 412 return -1;
413 } 413 }
414 414
415 415
416 // Format takes a formatting string for a whole instruction and prints it into 416 // Format takes a formatting string for a whole instruction and prints it into
417 // the output buffer. All escaped options are handed to FormatOption to be 417 // the output buffer. All escaped options are handed to FormatOption to be
418 // parsed further. 418 // parsed further.
419 void Decoder::Format(Instruction* instr, const char* format) { 419 void Decoder::Format(Instruction* instr, const char* format) {
420 char cur = *format++; 420 char cur = *format++;
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596 UNREACHABLE(); 596 UNREACHABLE();
597 } 597 }
598 break; 598 break;
599 case COP1X: 599 case COP1X:
600 switch (instr->FunctionFieldRaw()) { 600 switch (instr->FunctionFieldRaw()) {
601 case MADD_D: 601 case MADD_D:
602 Format(instr, "madd.d 'fd, 'fr, 'fs, 'ft"); 602 Format(instr, "madd.d 'fd, 'fr, 'fs, 'ft");
603 break; 603 break;
604 default: 604 default:
605 UNREACHABLE(); 605 UNREACHABLE();
606 }; 606 }
607 break; 607 break;
608 case SPECIAL: 608 case SPECIAL:
609 switch (instr->FunctionFieldRaw()) { 609 switch (instr->FunctionFieldRaw()) {
610 case JR: 610 case JR:
611 Format(instr, "jr 'rs"); 611 Format(instr, "jr 'rs");
612 break; 612 break;
613 case JALR: 613 case JALR:
614 Format(instr, "jalr 'rs"); 614 Format(instr, "jalr 'rs");
615 break; 615 break;
616 case SLL: 616 case SLL:
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789 switch (instr->RsFieldRaw()) { 789 switch (instr->RsFieldRaw()) {
790 case BC1: 790 case BC1:
791 if (instr->FBtrueValue()) { 791 if (instr->FBtrueValue()) {
792 Format(instr, "bc1t 'bc, 'imm16u"); 792 Format(instr, "bc1t 'bc, 'imm16u");
793 } else { 793 } else {
794 Format(instr, "bc1f 'bc, 'imm16u"); 794 Format(instr, "bc1f 'bc, 'imm16u");
795 } 795 }
796 break; 796 break;
797 default: 797 default:
798 UNREACHABLE(); 798 UNREACHABLE();
799 }; 799 }
800 break; // Case COP1. 800 break; // Case COP1.
801 case REGIMM: 801 case REGIMM:
802 switch (instr->RtFieldRaw()) { 802 switch (instr->RtFieldRaw()) {
803 case BLTZ: 803 case BLTZ:
804 Format(instr, "bltz 'rs, 'imm16u"); 804 Format(instr, "bltz 'rs, 'imm16u");
805 break; 805 break;
806 case BLTZAL: 806 case BLTZAL:
807 Format(instr, "bltzal 'rs, 'imm16u"); 807 Format(instr, "bltzal 'rs, 'imm16u");
808 break; 808 break;
809 case BGEZ: 809 case BGEZ:
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902 break; 902 break;
903 case SWC1: 903 case SWC1:
904 Format(instr, "swc1 'ft, 'imm16s('rs)"); 904 Format(instr, "swc1 'ft, 'imm16s('rs)");
905 break; 905 break;
906 case SDC1: 906 case SDC1:
907 Format(instr, "sdc1 'ft, 'imm16s('rs)"); 907 Format(instr, "sdc1 'ft, 'imm16s('rs)");
908 break; 908 break;
909 default: 909 default:
910 UNREACHABLE(); 910 UNREACHABLE();
911 break; 911 break;
912 }; 912 }
913 } 913 }
914 914
915 915
916 void Decoder::DecodeTypeJump(Instruction* instr) { 916 void Decoder::DecodeTypeJump(Instruction* instr) {
917 switch (instr->OpcodeFieldRaw()) { 917 switch (instr->OpcodeFieldRaw()) {
918 case J: 918 case J:
919 Format(instr, "j 'imm26x"); 919 Format(instr, "j 'imm26x");
920 break; 920 break;
921 case JAL: 921 case JAL:
922 Format(instr, "jal 'imm26x"); 922 Format(instr, "jal 'imm26x");
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1032 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); 1032 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
1033 } 1033 }
1034 } 1034 }
1035 1035
1036 1036
1037 #undef UNSUPPORTED 1037 #undef UNSUPPORTED
1038 1038
1039 } // namespace disasm 1039 } // namespace disasm
1040 1040
1041 #endif // V8_TARGET_ARCH_MIPS 1041 #endif // V8_TARGET_ARCH_MIPS
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