Presubmit checks recover.

src/mips/constants-mips.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "v8.h"
 
 #if V8_TARGET_ARCH_MIPS
 
 #include "constants-mips.h"
 
@@ skipping 133 matching lines @@
       return true;
     case REGIMM:
       switch (RtFieldRaw()) {
         case BLTZ:
         case BGEZ:
         case BLTZAL:
         case BGEZAL:
           return true;
         default:
           return false;
-      };
+      }
       break;
     case SPECIAL:
       switch (FunctionFieldRaw()) {
         case JR:
         case JALR:
           return true;
         default:
           return false;
-      };
+      }
       break;
     default:
       return false;
-  };
+  }
 }
 
 
 bool Instruction::IsLinkingInstruction() const {
   const int op = OpcodeFieldRaw();
   switch (op) {
     case JAL:
       return true;
     case REGIMM:
       switch (RtFieldRaw()) {
         case BGEZAL:
         case BLTZAL:
           return true;
       default:
         return false;
-      };
+      }
     case SPECIAL:
       switch (FunctionFieldRaw()) {
         case JALR:
           return true;
         default:
           return false;
-      };
+      }
     default:
       return false;
-  };
+  }
 }
 
 
 bool Instruction::IsTrap() const {
   if (OpcodeFieldRaw() != SPECIAL) {
     return false;
   } else {
     switch (FunctionFieldRaw()) {
       case BREAK:
       case TGE:
       case TGEU:
       case TLT:
       case TLTU:
       case TEQ:
       case TNE:
         return true;
       default:
         return false;
-    };
+    }
   }
 }
 
 
 Instruction::Type Instruction::InstructionType() const {
   switch (OpcodeFieldRaw()) {
     case SPECIAL:
       switch (FunctionFieldRaw()) {
         case JR:
         case JALR:
@@ skipping 25 matching lines @@
         case TLT:
         case TLTU:
         case TEQ:
         case TNE:
         case MOVZ:
         case MOVN:
         case MOVCI:
           return kRegisterType;
         default:
           return kUnsupported;
-      };
+      }
       break;
     case SPECIAL2:
       switch (FunctionFieldRaw()) {
         case MUL:
         case CLZ:
           return kRegisterType;
         default:
           return kUnsupported;
-      };
+      }
       break;
     case SPECIAL3:
       switch (FunctionFieldRaw()) {
         case INS:
         case EXT:
           return kRegisterType;
         default:
           return kUnsupported;
-      };
+      }
       break;
     case COP1:    // Coprocessor instructions.
       switch (RsFieldRawNoAssert()) {
         case BC1:   // Branch on coprocessor condition.
           return kImmediateType;
         default:
           return kRegisterType;
-      };
+      }
       break;
     case COP1X:
       return kRegisterType;
     // 16 bits Immediate type instructions. e.g.: addi dest, src, imm16.
     case REGIMM:
     case BEQ:
     case BNE:
     case BLEZ:
     case BGTZ:
     case ADDI:
@@ skipping 24 matching lines @@
     case LDC1:
     case SWC1:
     case SDC1:
       return kImmediateType;
     // 26 bits immediate type instructions. e.g.: j imm26.
     case J:
     case JAL:
       return kJumpType;
     default:
       return kUnsupported;
-  };
+  }
   return kUnsupported;
 }
 
 
 } }   // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_MIPS