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| 1 // Copyright 2013 the V8 project authors. All rights reserved. | 1 // Copyright 2013 the V8 project authors. All rights reserved. |
| 2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
| 3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
| 4 | 4 |
| 5 // CPU specific code for arm independent of OS goes here. | 5 // CPU specific code for arm independent of OS goes here. |
| 6 | 6 |
| 7 #include "v8.h" | 7 #include "v8.h" |
| 8 | 8 |
| 9 #if V8_TARGET_ARCH_ARM64 | 9 #if V8_TARGET_ARCH_ARM64 |
| 10 | 10 |
| (...skipping 14 matching lines...) Expand all Loading... |
| 25 class CacheLineSizes { | 25 class CacheLineSizes { |
| 26 public: | 26 public: |
| 27 CacheLineSizes() { | 27 CacheLineSizes() { |
| 28 #ifdef USE_SIMULATOR | 28 #ifdef USE_SIMULATOR |
| 29 cache_type_register_ = 0; | 29 cache_type_register_ = 0; |
| 30 #else | 30 #else |
| 31 // Copy the content of the cache type register to a core register. | 31 // Copy the content of the cache type register to a core register. |
| 32 __asm__ __volatile__ ("mrs %[ctr], ctr_el0" // NOLINT | 32 __asm__ __volatile__ ("mrs %[ctr], ctr_el0" // NOLINT |
| 33 : [ctr] "=r" (cache_type_register_)); | 33 : [ctr] "=r" (cache_type_register_)); |
| 34 #endif | 34 #endif |
| 35 }; | 35 } |
| 36 | 36 |
| 37 uint32_t icache_line_size() const { return ExtractCacheLineSize(0); } | 37 uint32_t icache_line_size() const { return ExtractCacheLineSize(0); } |
| 38 uint32_t dcache_line_size() const { return ExtractCacheLineSize(16); } | 38 uint32_t dcache_line_size() const { return ExtractCacheLineSize(16); } |
| 39 | 39 |
| 40 private: | 40 private: |
| 41 uint32_t ExtractCacheLineSize(int cache_line_size_shift) const { | 41 uint32_t ExtractCacheLineSize(int cache_line_size_shift) const { |
| 42 // The cache type register holds the size of the caches as a power of two. | 42 // The cache type register holds the size of the caches as a power of two. |
| 43 return 1 << ((cache_type_register_ >> cache_line_size_shift) & 0xf); | 43 return 1 << ((cache_type_register_ >> cache_line_size_shift) & 0xf); |
| 44 } | 44 } |
| 45 | 45 |
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| 149 | 149 |
| 150 #ifdef DEBUG | 150 #ifdef DEBUG |
| 151 initialized_ = true; | 151 initialized_ = true; |
| 152 #endif | 152 #endif |
| 153 } | 153 } |
| 154 | 154 |
| 155 | 155 |
| 156 } } // namespace v8::internal | 156 } } // namespace v8::internal |
| 157 | 157 |
| 158 #endif // V8_TARGET_ARCH_ARM64 | 158 #endif // V8_TARGET_ARCH_ARM64 |
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