MIPS[64]: Support for some SIMD operations (4)

src/compiler/mips64/instruction-codes-mips64.h

Index: src/compiler/mips64/instruction-codes-mips64.h
diff --git a/src/compiler/mips64/instruction-codes-mips64.h b/src/compiler/mips64/instruction-codes-mips64.h
index 5d22bc1eba0b7e333a1dfcc46468fe33b5623e31..386f8526591ae5b134a419368447a5f8b247b6f5 100644
--- a/src/compiler/mips64/instruction-codes-mips64.h
+++ b/src/compiler/mips64/instruction-codes-mips64.h
@@ -188,7 +188,24 @@ namespace compiler {
   V(Mips64I32x4ShrU)                \
   V(Mips64I32x4MaxU)                \
   V(Mips64I32x4MinU)                \
-  V(Mips64S32x4Select)
+  V(Mips64S32x4Select)              \
+  V(Mips64F32x4Abs)                 \
+  V(Mips64F32x4Neg)                 \
+  V(Mips64F32x4RecipApprox)         \
+  V(Mips64F32x4RecipRefine)         \
+  V(Mips64F32x4RecipSqrtApprox)     \
+  V(Mips64F32x4RecipSqrtRefine)     \
+  V(Mips64F32x4Add)                 \
+  V(Mips64F32x4Sub)                 \
+  V(Mips64F32x4Mul)                 \
+  V(Mips64F32x4Max)                 \
+  V(Mips64F32x4Min)                 \
+  V(Mips64F32x4Eq)                  \
+  V(Mips64F32x4Ne)                  \
+  V(Mips64F32x4Lt)                  \
+  V(Mips64F32x4Le)                  \
+  V(Mips64I32x4SConvertF32x4)       \
+  V(Mips64I32x4UConvertF32x4)
 
 // Addressing modes represent the "shape" of inputs to an instruction.
 // Many instructions support multiple addressing modes. Addressing modes