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Unified Diff: src/mips/assembler-mips.h

Issue 2778203002: MIPS[64]: Support for some SIMD operations (4) (Closed)
Patch Set: Created 3 years, 9 months ago
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« src/compiler/mips/code-generator-mips.cc ('K') | « src/compiler/mips64/instruction-selector-mips64.cc ('k') | src/mips64/assembler-mips64.h » ('j') | no next file with comments »
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Index: src/mips/assembler-mips.h
diff --git a/src/mips/assembler-mips.h b/src/mips/assembler-mips.h
index 61043eff643d7c9f5bb3e448b812afad4b2aa71c..6403f06e57a2e9c9d75609b6c47a7da1c8587f85 100644
--- a/src/mips/assembler-mips.h
+++ b/src/mips/assembler-mips.h
@@ -356,6 +356,9 @@ constexpr DoubleRegister kLithiumScratchDouble = f30;
constexpr DoubleRegister kDoubleRegZero = f28;
// Used on mips32r6 for compare operations.
constexpr DoubleRegister kDoubleCompareReg = f26;
+// MSA zero and scratch regs must have the same numbers as FPU zero and scratch
+constexpr Simd128Register kSimd128RegZero = w28;
+constexpr Simd128Register kSimd128ScratchReg = w30;
// FPU (coprocessor 1) control registers.
// Currently only FCSR (#31) is implemented.
« src/compiler/mips/code-generator-mips.cc ('K') | « src/compiler/mips64/instruction-selector-mips64.cc ('k') | src/mips64/assembler-mips64.h » ('j') | no next file with comments »

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