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Unified Diff: src/compiler/mips64/instruction-codes-mips64.h

Issue 2778203002: MIPS[64]: Support for some SIMD operations (4) (Closed)
Patch Set: Created 3 years, 9 months ago
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« src/compiler/mips/code-generator-mips.cc ('K') | « src/compiler/mips64/code-generator-mips64.cc ('k') | src/compiler/mips64/instruction-selector-mips64.cc » ('j') | no next file with comments »
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Index: src/compiler/mips64/instruction-codes-mips64.h
diff --git a/src/compiler/mips64/instruction-codes-mips64.h b/src/compiler/mips64/instruction-codes-mips64.h
index 0c0e1aa61e24c8f150bebfc6bc737f690baa684f..45fbe7134eebe443764b1efbcdf32167cf21eca5 100644
--- a/src/compiler/mips64/instruction-codes-mips64.h
+++ b/src/compiler/mips64/instruction-codes-mips64.h
@@ -166,7 +166,24 @@ namespace compiler {
V(Mips64StackClaim) \
V(Mips64Seb) \
V(Mips64Seh) \
- V(Mips64AssertEqual)
+ V(Mips64AssertEqual) \
+ V(Mips64Float32x4Abs) \
+ V(Mips64Float32x4Neg) \
+ V(Mips64Float32x4RecipApprox) \
+ V(Mips64Float32x4RecipRefine) \
+ V(Mips64Float32x4RecipSqrtApprox) \
+ V(Mips64Float32x4RecipSqrtRefine) \
+ V(Mips64Float32x4Add) \
+ V(Mips64Float32x4Sub) \
+ V(Mips64Float32x4Mul) \
+ V(Mips64Float32x4Max) \
+ V(Mips64Float32x4Min) \
+ V(Mips64Float32xEqual) \
+ V(Mips64Float32x4NotEqual) \
+ V(Mips64Float32xLessThan) \
+ V(Mips64Float32xLessThanOrEqual) \
+ V(Mips64Int32x4FromFloat32x4) \
+ V(Mips64Uint32x4FromFloat32x4)
// Addressing modes represent the "shape" of inputs to an instruction.
// Many instructions support multiple addressing modes. Addressing modes
« src/compiler/mips/code-generator-mips.cc ('K') | « src/compiler/mips64/code-generator-mips64.cc ('k') | src/compiler/mips64/instruction-selector-mips64.cc » ('j') | no next file with comments »

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