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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ | 5 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ | 6 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
7 | 7 |
8 namespace v8 { | 8 namespace v8 { |
9 namespace internal { | 9 namespace internal { |
10 namespace compiler { | 10 namespace compiler { |
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147 V(MipsI32x4Mul) \ | 147 V(MipsI32x4Mul) \ |
148 V(MipsI32x4MaxS) \ | 148 V(MipsI32x4MaxS) \ |
149 V(MipsI32x4MinS) \ | 149 V(MipsI32x4MinS) \ |
150 V(MipsI32x4Eq) \ | 150 V(MipsI32x4Eq) \ |
151 V(MipsI32x4Ne) \ | 151 V(MipsI32x4Ne) \ |
152 V(MipsI32x4Shl) \ | 152 V(MipsI32x4Shl) \ |
153 V(MipsI32x4ShrS) \ | 153 V(MipsI32x4ShrS) \ |
154 V(MipsI32x4ShrU) \ | 154 V(MipsI32x4ShrU) \ |
155 V(MipsI32x4MaxU) \ | 155 V(MipsI32x4MaxU) \ |
156 V(MipsI32x4MinU) \ | 156 V(MipsI32x4MinU) \ |
157 V(MipsS32x4Select) | 157 V(MipsS32x4Select) \ |
| 158 V(MipsF32x4Abs) \ |
| 159 V(MipsF32x4Neg) \ |
| 160 V(MipsF32x4RecipApprox) \ |
| 161 V(MipsF32x4RecipRefine) \ |
| 162 V(MipsF32x4RecipSqrtApprox) \ |
| 163 V(MipsF32x4RecipSqrtRefine) \ |
| 164 V(MipsF32x4Add) \ |
| 165 V(MipsF32x4Sub) \ |
| 166 V(MipsF32x4Mul) \ |
| 167 V(MipsF32x4Max) \ |
| 168 V(MipsF32x4Min) \ |
| 169 V(MipsF32x4Eq) \ |
| 170 V(MipsF32x4Ne) \ |
| 171 V(MipsF32x4Lt) \ |
| 172 V(MipsF32x4Le) \ |
| 173 V(MipsI32x4SConvertF32x4) \ |
| 174 V(MipsI32x4UConvertF32x4) |
158 | 175 |
159 // Addressing modes represent the "shape" of inputs to an instruction. | 176 // Addressing modes represent the "shape" of inputs to an instruction. |
160 // Many instructions support multiple addressing modes. Addressing modes | 177 // Many instructions support multiple addressing modes. Addressing modes |
161 // are encoded into the InstructionCode of the instruction and tell the | 178 // are encoded into the InstructionCode of the instruction and tell the |
162 // code generator after register allocation which assembler method to call. | 179 // code generator after register allocation which assembler method to call. |
163 // | 180 // |
164 // We use the following local notation for addressing modes: | 181 // We use the following local notation for addressing modes: |
165 // | 182 // |
166 // R = register | 183 // R = register |
167 // O = register or stack slot | 184 // O = register or stack slot |
168 // D = double register | 185 // D = double register |
169 // I = immediate (handle, external, int32) | 186 // I = immediate (handle, external, int32) |
170 // MRI = [register + immediate] | 187 // MRI = [register + immediate] |
171 // MRR = [register + register] | 188 // MRR = [register + register] |
172 // TODO(plind): Add the new r6 address modes. | 189 // TODO(plind): Add the new r6 address modes. |
173 #define TARGET_ADDRESSING_MODE_LIST(V) \ | 190 #define TARGET_ADDRESSING_MODE_LIST(V) \ |
174 V(MRI) /* [%r0 + K] */ \ | 191 V(MRI) /* [%r0 + K] */ \ |
175 V(MRR) /* [%r0 + %r1] */ | 192 V(MRR) /* [%r0 + %r1] */ |
176 | 193 |
177 | 194 |
178 } // namespace compiler | 195 } // namespace compiler |
179 } // namespace internal | 196 } // namespace internal |
180 } // namespace v8 | 197 } // namespace v8 |
181 | 198 |
182 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ | 199 #endif // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_ |
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