MIPS[64]: Support for some SIMD operations (4)

src/compiler/mips64/instruction-codes-mips64.h

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
 #define V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_
 
 namespace v8 {
 namespace internal {
 namespace compiler {
@@ skipping 148 matching lines @@
   V(Mips64Float32Min)               \
   V(Mips64Float64Min)               \
   V(Mips64Float64SilenceNaN)        \
   V(Mips64Push)                     \
   V(Mips64StoreToStackSlot)         \
   V(Mips64ByteSwap64)               \
   V(Mips64ByteSwap32)               \
   V(Mips64StackClaim)               \
   V(Mips64Seb)                      \
   V(Mips64Seh)                      \
-  V(Mips64AssertEqual)
+  V(Mips64AssertEqual)              \
+  V(Mips64Float32x4Abs)             \
+  V(Mips64Float32x4Neg)             \
+  V(Mips64Float32x4RecipApprox)     \
+  V(Mips64Float32x4RecipRefine)     \
+  V(Mips64Float32x4RecipSqrtApprox) \
+  V(Mips64Float32x4RecipSqrtRefine) \
+  V(Mips64Float32x4Add)             \
+  V(Mips64Float32x4Sub)             \
+  V(Mips64Float32x4Mul)             \
+  V(Mips64Float32x4Max)             \
+  V(Mips64Float32x4Min)             \
+  V(Mips64Float32xEqual)            \
+  V(Mips64Float32x4NotEqual)        \
+  V(Mips64Float32xLessThan)         \
+  V(Mips64Float32xLessThanOrEqual)  \
+  V(Mips64Int32x4FromFloat32x4)     \
+  V(Mips64Uint32x4FromFloat32x4)
 
 // Addressing modes represent the "shape" of inputs to an instruction.
 // Many instructions support multiple addressing modes. Addressing modes
 // are encoded into the InstructionCode of the instruction and tell the
 // code generator after register allocation which assembler method to call.
 //
 // We use the following local notation for addressing modes:
 //
 // R = register
 // O = register or stack slot
 // D = double register
 // I = immediate (handle, external, int32)
 // MRI = [register + immediate]
 // MRR = [register + register]
 // TODO(plind): Add the new r6 address modes.
 #define TARGET_ADDRESSING_MODE_LIST(V) \
   V(MRI) /* [%r0 + K] */               \
   V(MRR) /* [%r0 + %r1] */
 
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_COMPILER_MIPS_INSTRUCTION_CODES_MIPS_H_