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Unified Diff: src/compiler/arm/instruction-codes-arm.h

Issue 2776753004: [wasm] Make Opcode names consistent across architectures, implementations (Closed)
Patch Set: Fix convert order Created 3 years, 9 months ago
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« src/compiler/arm/code-generator-arm.cc ('K') | « src/compiler/arm/code-generator-arm.cc ('k') | src/compiler/arm/instruction-scheduler-arm.cc » ('j') | no next file with comments »
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Index: src/compiler/arm/instruction-codes-arm.h
diff --git a/src/compiler/arm/instruction-codes-arm.h b/src/compiler/arm/instruction-codes-arm.h
index 5a05c4bfa0ac068cbbdfb8585381a6f0e01c25f8..6e5c7d9ee8cd7e2dbe9a1bc77451c0915d99e3f4 100644
--- a/src/compiler/arm/instruction-codes-arm.h
+++ b/src/compiler/arm/instruction-codes-arm.h
@@ -124,108 +124,108 @@ namespace compiler {
V(ArmStr) \
V(ArmPush) \
V(ArmPoke) \
- V(ArmFloat32x4Splat) \
- V(ArmFloat32x4ExtractLane) \
- V(ArmFloat32x4ReplaceLane) \
- V(ArmFloat32x4FromInt32x4) \
- V(ArmFloat32x4FromUint32x4) \
- V(ArmFloat32x4Abs) \
- V(ArmFloat32x4Neg) \
- V(ArmFloat32x4RecipApprox) \
- V(ArmFloat32x4RecipSqrtApprox) \
- V(ArmFloat32x4Add) \
- V(ArmFloat32x4Sub) \
- V(ArmFloat32x4Mul) \
- V(ArmFloat32x4Min) \
- V(ArmFloat32x4Max) \
- V(ArmFloat32x4RecipRefine) \
- V(ArmFloat32x4RecipSqrtRefine) \
- V(ArmFloat32x4Equal) \
- V(ArmFloat32x4NotEqual) \
- V(ArmFloat32x4LessThan) \
- V(ArmFloat32x4LessThanOrEqual) \
- V(ArmInt32x4Splat) \
- V(ArmInt32x4ExtractLane) \
- V(ArmInt32x4ReplaceLane) \
- V(ArmInt32x4FromFloat32x4) \
- V(ArmUint32x4FromFloat32x4) \
- V(ArmInt32x4Neg) \
- V(ArmInt32x4ShiftLeftByScalar) \
- V(ArmInt32x4ShiftRightByScalar) \
- V(ArmInt32x4Add) \
- V(ArmInt32x4Sub) \
- V(ArmInt32x4Mul) \
- V(ArmInt32x4Min) \
- V(ArmInt32x4Max) \
- V(ArmInt32x4Equal) \
- V(ArmInt32x4NotEqual) \
- V(ArmInt32x4LessThan) \
- V(ArmInt32x4LessThanOrEqual) \
- V(ArmUint32x4ShiftRightByScalar) \
- V(ArmUint32x4Min) \
- V(ArmUint32x4Max) \
- V(ArmUint32x4LessThan) \
- V(ArmUint32x4LessThanOrEqual) \
- V(ArmInt16x8Splat) \
- V(ArmInt16x8ExtractLane) \
- V(ArmInt16x8ReplaceLane) \
- V(ArmInt16x8Neg) \
- V(ArmInt16x8ShiftLeftByScalar) \
- V(ArmInt16x8ShiftRightByScalar) \
- V(ArmInt16x8Add) \
- V(ArmInt16x8AddSaturate) \
- V(ArmInt16x8Sub) \
- V(ArmInt16x8SubSaturate) \
- V(ArmInt16x8Mul) \
- V(ArmInt16x8Min) \
- V(ArmInt16x8Max) \
- V(ArmInt16x8Equal) \
- V(ArmInt16x8NotEqual) \
- V(ArmInt16x8LessThan) \
- V(ArmInt16x8LessThanOrEqual) \
- V(ArmUint16x8ShiftRightByScalar) \
- V(ArmUint16x8AddSaturate) \
- V(ArmUint16x8SubSaturate) \
- V(ArmUint16x8Min) \
- V(ArmUint16x8Max) \
- V(ArmUint16x8LessThan) \
- V(ArmUint16x8LessThanOrEqual) \
- V(ArmInt8x16Splat) \
- V(ArmInt8x16ExtractLane) \
- V(ArmInt8x16ReplaceLane) \
- V(ArmInt8x16Neg) \
- V(ArmInt8x16ShiftLeftByScalar) \
- V(ArmInt8x16ShiftRightByScalar) \
- V(ArmInt8x16Add) \
- V(ArmInt8x16AddSaturate) \
- V(ArmInt8x16Sub) \
- V(ArmInt8x16SubSaturate) \
- V(ArmInt8x16Mul) \
- V(ArmInt8x16Min) \
- V(ArmInt8x16Max) \
- V(ArmInt8x16Equal) \
- V(ArmInt8x16NotEqual) \
- V(ArmInt8x16LessThan) \
- V(ArmInt8x16LessThanOrEqual) \
- V(ArmUint8x16ShiftRightByScalar) \
- V(ArmUint8x16AddSaturate) \
- V(ArmUint8x16SubSaturate) \
- V(ArmUint8x16Min) \
- V(ArmUint8x16Max) \
- V(ArmUint8x16LessThan) \
- V(ArmUint8x16LessThanOrEqual) \
- V(ArmSimd128Zero) \
- V(ArmSimd128And) \
- V(ArmSimd128Or) \
- V(ArmSimd128Xor) \
- V(ArmSimd128Not) \
- V(ArmSimd128Select) \
- V(ArmSimd1x4AnyTrue) \
- V(ArmSimd1x4AllTrue) \
- V(ArmSimd1x8AnyTrue) \
- V(ArmSimd1x8AllTrue) \
- V(ArmSimd1x16AnyTrue) \
- V(ArmSimd1x16AllTrue)
+ V(ArmF32x4Splat) \
+ V(ArmF32x4ExtractLane) \
+ V(ArmF32x4ReplaceLane) \
+ V(ArmF32x4SConvertI32x4) \
+ V(ArmF32x4UConvertI32x4) \
+ V(ArmF32x4Abs) \
+ V(ArmF32x4Neg) \
+ V(ArmF32x4RecipApprox) \
+ V(ArmF32x4RecipSqrtApprox) \
+ V(ArmF32x4Add) \
+ V(ArmF32x4Sub) \
+ V(ArmF32x4Mul) \
+ V(ArmF32x4Min) \
+ V(ArmF32x4Max) \
+ V(ArmF32x4RecipRefine) \
+ V(ArmF32x4RecipSqrtRefine) \
+ V(ArmF32x4Eq) \
+ V(ArmF32x4Ne) \
+ V(ArmF32x4Lt) \
+ V(ArmF32x4Le) \
+ V(ArmI32x4Splat) \
+ V(ArmI32x4ExtractLane) \
+ V(ArmI32x4ReplaceLane) \
+ V(ArmI32x4SConvertF32x4) \
+ V(ArmI32x4Neg) \
+ V(ArmI32x4Shl) \
+ V(ArmI32x4ShrS) \
+ V(ArmI32x4Add) \
+ V(ArmI32x4Sub) \
+ V(ArmI32x4Mul) \
+ V(ArmI32x4MinS) \
+ V(ArmI32x4MaxS) \
+ V(ArmI32x4Eq) \
+ V(ArmI32x4Ne) \
+ V(ArmI32x4LtS) \
+ V(ArmI32x4LeS) \
+ V(ArmI32x4UConvertF32x4) \
+ V(ArmI32x4ShrU) \
+ V(ArmI32x4MinU) \
+ V(ArmI32x4MaxU) \
+ V(ArmI32x4LtU) \
+ V(ArmI32x4LeU) \
+ V(ArmI16x8Splat) \
+ V(ArmI16x8ExtractLane) \
+ V(ArmI16x8ReplaceLane) \
+ V(ArmI16x8Neg) \
+ V(ArmI16x8Shl) \
+ V(ArmI16x8ShrS) \
+ V(ArmI16x8Add) \
+ V(ArmI16x8AddSaturate) \
+ V(ArmI16x8Sub) \
+ V(ArmI16x8SubSaturate) \
+ V(ArmI16x8Mul) \
+ V(ArmI16x8MinS) \
+ V(ArmI16x8MaxS) \
+ V(ArmI16x8Eq) \
+ V(ArmI16x8Ne) \
+ V(ArmI16x8LtS) \
+ V(ArmI16x8LeS) \
+ V(ArmI16x8ShrU) \
+ V(ArmI16x8AddSaturateU) \
+ V(ArmI16x8SubSaturateU) \
+ V(ArmI16x8MinU) \
+ V(ArmI16x8MaxU) \
+ V(ArmI16x8LtU) \
+ V(ArmI16x8LeU) \
+ V(ArmI8x16Splat) \
+ V(ArmI8x16ExtractLane) \
+ V(ArmI8x16ReplaceLane) \
+ V(ArmI8x16Neg) \
+ V(ArmI8x16Shl) \
+ V(ArmI8x16ShrS) \
+ V(ArmI8x16Add) \
+ V(ArmI8x16AddSaturate) \
+ V(ArmI8x16Sub) \
+ V(ArmI8x16SubSaturate) \
+ V(ArmI8x16Mul) \
+ V(ArmI8x16MinS) \
+ V(ArmI8x16MaxS) \
+ V(ArmI8x16Eq) \
+ V(ArmI8x16Ne) \
+ V(ArmI8x16LtS) \
+ V(ArmI8x16LeS) \
+ V(ArmI8x16ShrU) \
+ V(ArmI8x16AddSaturateU) \
+ V(ArmI8x16SubSaturateU) \
+ V(ArmI8x16MinU) \
+ V(ArmI8x16MaxU) \
+ V(ArmI8x16LtU) \
+ V(ArmI8x16LeU) \
+ V(ArmS128Zero) \
+ V(ArmS128And) \
+ V(ArmS128Or) \
+ V(ArmS128Xor) \
+ V(ArmS128Not) \
+ V(ArmS128Select) \
+ V(ArmS1x4AnyTrue) \
+ V(ArmS1x4AllTrue) \
+ V(ArmS1x8AnyTrue) \
+ V(ArmS1x8AllTrue) \
+ V(ArmS1x16AnyTrue) \
+ V(ArmS1x16AllTrue)
// Addressing modes represent the "shape" of inputs to an instruction.
// Many instructions support multiple addressing modes. Addressing modes
« src/compiler/arm/code-generator-arm.cc ('K') | « src/compiler/arm/code-generator-arm.cc ('k') | src/compiler/arm/instruction-scheduler-arm.cc » ('j') | no next file with comments »

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