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Side by Side Diff: src/compiler/opcodes.h

Issue 2776753004: [wasm] Make Opcode names consistent across architectures, implementations (Closed)
Patch Set: Fix missing Convert Created 3 years, 8 months ago
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1 // Copyright 2013 the V8 project authors. All rights reserved. 1 // Copyright 2013 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_OPCODES_H_ 5 #ifndef V8_COMPILER_OPCODES_H_
6 #define V8_COMPILER_OPCODES_H_ 6 #define V8_COMPILER_OPCODES_H_
7 7
8 #include <iosfwd> 8 #include <iosfwd>
9 9
10 #include "src/globals.h" 10 #include "src/globals.h"
(...skipping 539 matching lines...) Expand 10 before | Expand all | Expand 10 after
550 V(Word32PairShr) \ 550 V(Word32PairShr) \
551 V(Word32PairSar) \ 551 V(Word32PairSar) \
552 V(ProtectedLoad) \ 552 V(ProtectedLoad) \
553 V(ProtectedStore) \ 553 V(ProtectedStore) \
554 V(AtomicLoad) \ 554 V(AtomicLoad) \
555 V(AtomicStore) \ 555 V(AtomicStore) \
556 V(AtomicExchange) \ 556 V(AtomicExchange) \
557 V(AtomicCompareExchange) \ 557 V(AtomicCompareExchange) \
558 V(UnsafePointerAdd) 558 V(UnsafePointerAdd)
559 559
560 #define MACHINE_SIMD_OP_LIST(V) \ 560 #define MACHINE_SIMD_OP_LIST(V) \
561 V(Float32x4Splat) \ 561 V(F32x4Splat) \
562 V(Float32x4ExtractLane) \ 562 V(F32x4ExtractLane) \
563 V(Float32x4ReplaceLane) \ 563 V(F32x4ReplaceLane) \
564 V(Float32x4Abs) \ 564 V(F32x4SConvertI32x4) \
565 V(Float32x4Neg) \ 565 V(F32x4UConvertI32x4) \
566 V(Float32x4Sqrt) \ 566 V(F32x4Abs) \
567 V(Float32x4RecipApprox) \ 567 V(F32x4Neg) \
568 V(Float32x4RecipSqrtApprox) \ 568 V(F32x4Sqrt) \
569 V(Float32x4Add) \ 569 V(F32x4RecipApprox) \
570 V(Float32x4Sub) \ 570 V(F32x4RecipSqrtApprox) \
571 V(Float32x4Mul) \ 571 V(F32x4Add) \
572 V(Float32x4Div) \ 572 V(F32x4Sub) \
573 V(Float32x4Min) \ 573 V(F32x4Mul) \
574 V(Float32x4Max) \ 574 V(F32x4Div) \
575 V(Float32x4MinNum) \ 575 V(F32x4Min) \
576 V(Float32x4MaxNum) \ 576 V(F32x4Max) \
577 V(Float32x4RecipRefine) \ 577 V(F32x4MinNum) \
578 V(Float32x4RecipSqrtRefine) \ 578 V(F32x4MaxNum) \
579 V(Float32x4Equal) \ 579 V(F32x4RecipRefine) \
580 V(Float32x4NotEqual) \ 580 V(F32x4RecipSqrtRefine) \
581 V(Float32x4LessThan) \ 581 V(F32x4Eq) \
582 V(Float32x4LessThanOrEqual) \ 582 V(F32x4Ne) \
583 V(Float32x4GreaterThan) \ 583 V(F32x4Lt) \
584 V(Float32x4GreaterThanOrEqual) \ 584 V(F32x4Le) \
585 V(Float32x4FromInt32x4) \ 585 V(F32x4Gt) \
586 V(Float32x4FromUint32x4) \ 586 V(F32x4Ge) \
587 V(Int32x4Splat) \ 587 V(I32x4Splat) \
588 V(Int32x4ExtractLane) \ 588 V(I32x4ExtractLane) \
589 V(Int32x4ReplaceLane) \ 589 V(I32x4ReplaceLane) \
590 V(Int32x4Neg) \ 590 V(I32x4SConvertF32x4) \
591 V(Int32x4Add) \ 591 V(I32x4Neg) \
592 V(Int32x4Sub) \ 592 V(I32x4Shl) \
593 V(Int32x4Mul) \ 593 V(I32x4ShrS) \
594 V(Int32x4Min) \ 594 V(I32x4Add) \
595 V(Int32x4Max) \ 595 V(I32x4Sub) \
596 V(Int32x4ShiftLeftByScalar) \ 596 V(I32x4Mul) \
597 V(Int32x4ShiftRightByScalar) \ 597 V(I32x4MinS) \
598 V(Int32x4Equal) \ 598 V(I32x4MaxS) \
599 V(Int32x4NotEqual) \ 599 V(I32x4Eq) \
600 V(Int32x4LessThan) \ 600 V(I32x4Ne) \
601 V(Int32x4LessThanOrEqual) \ 601 V(I32x4LtS) \
602 V(Int32x4GreaterThan) \ 602 V(I32x4LeS) \
603 V(Int32x4GreaterThanOrEqual) \ 603 V(I32x4GtS) \
604 V(Int32x4FromFloat32x4) \ 604 V(I32x4GeS) \
605 V(Uint32x4Min) \ 605 V(I32x4UConvertF32x4) \
606 V(Uint32x4Max) \ 606 V(I32x4ShrU) \
607 V(Uint32x4ShiftLeftByScalar) \ 607 V(I32x4MinU) \
608 V(Uint32x4ShiftRightByScalar) \ 608 V(I32x4MaxU) \
609 V(Uint32x4LessThan) \ 609 V(I32x4LtU) \
610 V(Uint32x4LessThanOrEqual) \ 610 V(I32x4LeU) \
611 V(Uint32x4GreaterThan) \ 611 V(I32x4GtU) \
612 V(Uint32x4GreaterThanOrEqual) \ 612 V(I32x4GeU) \
613 V(Uint32x4FromFloat32x4) \ 613 V(I16x8Splat) \
614 V(Int16x8Splat) \ 614 V(I16x8ExtractLane) \
615 V(Int16x8ExtractLane) \ 615 V(I16x8ReplaceLane) \
616 V(Int16x8ReplaceLane) \ 616 V(I16x8Neg) \
617 V(Int16x8Neg) \ 617 V(I16x8Shl) \
618 V(Int16x8Add) \ 618 V(I16x8ShrS) \
619 V(Int16x8AddSaturate) \ 619 V(I16x8Add) \
620 V(Int16x8Sub) \ 620 V(I16x8AddSaturate) \
621 V(Int16x8SubSaturate) \ 621 V(I16x8Sub) \
622 V(Int16x8Mul) \ 622 V(I16x8SubSaturate) \
623 V(Int16x8Min) \ 623 V(I16x8Mul) \
624 V(Int16x8Max) \ 624 V(I16x8MinS) \
625 V(Int16x8ShiftLeftByScalar) \ 625 V(I16x8MaxS) \
626 V(Int16x8ShiftRightByScalar) \ 626 V(I16x8Eq) \
627 V(Int16x8Equal) \ 627 V(I16x8Ne) \
628 V(Int16x8NotEqual) \ 628 V(I16x8LtS) \
629 V(Int16x8LessThan) \ 629 V(I16x8LeS) \
630 V(Int16x8LessThanOrEqual) \ 630 V(I16x8GtS) \
631 V(Int16x8GreaterThan) \ 631 V(I16x8GeS) \
632 V(Int16x8GreaterThanOrEqual) \ 632 V(I16x8AddSaturateU) \
633 V(Uint16x8AddSaturate) \ 633 V(I16x8SubSaturateU) \
634 V(Uint16x8SubSaturate) \ 634 V(I16x8ShrU) \
635 V(Uint16x8Min) \ 635 V(I16x8MinU) \
636 V(Uint16x8Max) \ 636 V(I16x8MaxU) \
637 V(Uint16x8ShiftLeftByScalar) \ 637 V(I16x8LtU) \
638 V(Uint16x8ShiftRightByScalar) \ 638 V(I16x8LeU) \
639 V(Uint16x8LessThan) \ 639 V(I16x8GtU) \
640 V(Uint16x8LessThanOrEqual) \ 640 V(I16x8GeU) \
641 V(Uint16x8GreaterThan) \ 641 V(I8x16Splat) \
642 V(Uint16x8GreaterThanOrEqual) \ 642 V(I8x16ExtractLane) \
643 V(Int8x16Splat) \ 643 V(I8x16ReplaceLane) \
644 V(Int8x16ExtractLane) \ 644 V(I8x16Neg) \
645 V(Int8x16ReplaceLane) \ 645 V(I8x16Shl) \
646 V(Int8x16Neg) \ 646 V(I8x16ShrS) \
647 V(Int8x16Add) \ 647 V(I8x16Add) \
648 V(Int8x16AddSaturate) \ 648 V(I8x16AddSaturate) \
649 V(Int8x16Sub) \ 649 V(I8x16Sub) \
650 V(Int8x16SubSaturate) \ 650 V(I8x16SubSaturate) \
651 V(Int8x16Mul) \ 651 V(I8x16Mul) \
652 V(Int8x16Min) \ 652 V(I8x16MinS) \
653 V(Int8x16Max) \ 653 V(I8x16MaxS) \
654 V(Int8x16ShiftLeftByScalar) \ 654 V(I8x16Eq) \
655 V(Int8x16ShiftRightByScalar) \ 655 V(I8x16Ne) \
656 V(Int8x16Equal) \ 656 V(I8x16LtS) \
657 V(Int8x16NotEqual) \ 657 V(I8x16LeS) \
658 V(Int8x16LessThan) \ 658 V(I8x16GtS) \
659 V(Int8x16LessThanOrEqual) \ 659 V(I8x16GeS) \
660 V(Int8x16GreaterThan) \ 660 V(I8x16AddSaturateU) \
661 V(Int8x16GreaterThanOrEqual) \ 661 V(I8x16SubSaturateU) \
662 V(Uint8x16AddSaturate) \ 662 V(I8x16ShrU) \
663 V(Uint8x16SubSaturate) \ 663 V(I8x16MinU) \
664 V(Uint8x16Min) \ 664 V(I8x16MaxU) \
665 V(Uint8x16Max) \ 665 V(I8x16LtU) \
666 V(Uint8x16ShiftLeftByScalar) \ 666 V(I8x16LeU) \
667 V(Uint8x16ShiftRightByScalar) \ 667 V(I8x16GtU) \
668 V(Uint8x16LessThan) \ 668 V(I8x16GeU) \
669 V(Uint8x16LessThanOrEqual) \ 669 V(S128Load) \
670 V(Uint8x16GreaterThan) \ 670 V(S128Store) \
671 V(Uint8x16GreaterThanOrEqual) \ 671 V(S128Zero) \
672 V(Simd128Load) \ 672 V(S128And) \
673 V(Simd128Load1) \ 673 V(S128Or) \
674 V(Simd128Load2) \ 674 V(S128Xor) \
675 V(Simd128Load3) \ 675 V(S128Not) \
676 V(Simd128Store) \ 676 V(S32x4Select) \
677 V(Simd128Store1) \ 677 V(S32x4Swizzle) \
678 V(Simd128Store2) \ 678 V(S32x4Shuffle) \
679 V(Simd128Store3) \ 679 V(S16x8Select) \
680 V(Simd128Zero) \ 680 V(S16x8Swizzle) \
681 V(Simd128And) \ 681 V(S16x8Shuffle) \
682 V(Simd128Or) \ 682 V(S8x16Select) \
683 V(Simd128Xor) \ 683 V(S8x16Swizzle) \
684 V(Simd128Not) \ 684 V(S8x16Shuffle) \
685 V(Simd32x4Select) \ 685 V(S1x4Zero) \
686 V(Simd32x4Swizzle) \ 686 V(S1x4And) \
687 V(Simd32x4Shuffle) \ 687 V(S1x4Or) \
688 V(Simd16x8Select) \ 688 V(S1x4Xor) \
689 V(Simd16x8Swizzle) \ 689 V(S1x4Not) \
690 V(Simd16x8Shuffle) \ 690 V(S1x4AnyTrue) \
691 V(Simd8x16Select) \ 691 V(S1x4AllTrue) \
692 V(Simd8x16Swizzle) \ 692 V(S1x8Zero) \
693 V(Simd8x16Shuffle) \ 693 V(S1x8And) \
694 V(Simd1x4Zero) \ 694 V(S1x8Or) \
695 V(Simd1x4And) \ 695 V(S1x8Xor) \
696 V(Simd1x4Or) \ 696 V(S1x8Not) \
697 V(Simd1x4Xor) \ 697 V(S1x8AnyTrue) \
698 V(Simd1x4Not) \ 698 V(S1x8AllTrue) \
699 V(Simd1x4AnyTrue) \ 699 V(S1x16Zero) \
700 V(Simd1x4AllTrue) \ 700 V(S1x16And) \
701 V(Simd1x8Zero) \ 701 V(S1x16Or) \
702 V(Simd1x8And) \ 702 V(S1x16Xor) \
703 V(Simd1x8Or) \ 703 V(S1x16Not) \
704 V(Simd1x8Xor) \ 704 V(S1x16AnyTrue) \
705 V(Simd1x8Not) \ 705 V(S1x16AllTrue)
706 V(Simd1x8AnyTrue) \
707 V(Simd1x8AllTrue) \
708 V(Simd1x16Zero) \
709 V(Simd1x16And) \
710 V(Simd1x16Or) \
711 V(Simd1x16Xor) \
712 V(Simd1x16Not) \
713 V(Simd1x16AnyTrue) \
714 V(Simd1x16AllTrue)
715 706
716 #define VALUE_OP_LIST(V) \ 707 #define VALUE_OP_LIST(V) \
717 COMMON_OP_LIST(V) \ 708 COMMON_OP_LIST(V) \
718 SIMPLIFIED_OP_LIST(V) \ 709 SIMPLIFIED_OP_LIST(V) \
719 MACHINE_OP_LIST(V) \ 710 MACHINE_OP_LIST(V) \
720 MACHINE_SIMD_OP_LIST(V) \ 711 MACHINE_SIMD_OP_LIST(V) \
721 JS_OP_LIST(V) 712 JS_OP_LIST(V)
722 713
723 // The combination of all operators at all levels and the common operators. 714 // The combination of all operators at all levels and the common operators.
724 #define ALL_OP_LIST(V) \ 715 #define ALL_OP_LIST(V) \
(...skipping 77 matching lines...) Expand 10 before | Expand all | Expand 10 after
802 } 793 }
803 }; 794 };
804 795
805 V8_EXPORT_PRIVATE std::ostream& operator<<(std::ostream&, IrOpcode::Value); 796 V8_EXPORT_PRIVATE std::ostream& operator<<(std::ostream&, IrOpcode::Value);
806 797
807 } // namespace compiler 798 } // namespace compiler
808 } // namespace internal 799 } // namespace internal
809 } // namespace v8 800 } // namespace v8
810 801
811 #endif // V8_COMPILER_OPCODES_H_ 802 #endif // V8_COMPILER_OPCODES_H_
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