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Issue 2776753004: [wasm] Make Opcode names consistent across architectures, implementations (Closed)
Patch Set: Fix convert order Created 3 years, 8 months ago
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "src/base/adapters.h" 5 #include "src/base/adapters.h"
6 #include "src/base/bits.h" 6 #include "src/base/bits.h"
7 #include "src/compiler/instruction-selector-impl.h" 7 #include "src/compiler/instruction-selector-impl.h"
8 #include "src/compiler/node-matchers.h" 8 #include "src/compiler/node-matchers.h"
9 #include "src/compiler/node-properties.h" 9 #include "src/compiler/node-properties.h"
10 10
(...skipping 2286 matching lines...) Expand 10 before | Expand all | Expand 10 after
2297 InstructionOperand outputs[1]; 2297 InstructionOperand outputs[1];
2298 outputs[0] = g.UseUniqueRegister(node); 2298 outputs[0] = g.UseUniqueRegister(node);
2299 InstructionOperand temp[2]; 2299 InstructionOperand temp[2];
2300 temp[0] = g.TempRegister(); 2300 temp[0] = g.TempRegister();
2301 temp[1] = g.TempRegister(); 2301 temp[1] = g.TempRegister();
2302 InstructionCode code = opcode | AddressingModeField::encode(addressing_mode); 2302 InstructionCode code = opcode | AddressingModeField::encode(addressing_mode);
2303 Emit(code, 1, outputs, input_count, inputs, 2, temp); 2303 Emit(code, 1, outputs, input_count, inputs, 2, temp);
2304 } 2304 }
2305 2305
2306 #define SIMD_TYPE_LIST(V) \ 2306 #define SIMD_TYPE_LIST(V) \
2307 V(Float32x4) \ 2307 V(F32x4) \
2308 V(Int32x4) \ 2308 V(I32x4) \
2309 V(Int16x8) \ 2309 V(I16x8) \
2310 V(Int8x16) 2310 V(I8x16)
2311 2311
2312 #define SIMD_FORMAT_LIST(V) \ 2312 #define SIMD_FORMAT_LIST(V) \
2313 V(32x4) \ 2313 V(32x4) \
2314 V(16x8) \ 2314 V(16x8) \
2315 V(8x16) 2315 V(8x16)
2316 2316
2317 #define SIMD_ZERO_OP_LIST(V) \ 2317 #define SIMD_ZERO_OP_LIST(V) \
2318 V(Simd128Zero) \ 2318 V(S128Zero) \
2319 V(Simd1x4Zero) \ 2319 V(S1x4Zero) \
2320 V(Simd1x8Zero) \ 2320 V(S1x8Zero) \
2321 V(Simd1x16Zero) 2321 V(S1x16Zero)
2322 2322
2323 #define SIMD_UNOP_LIST(V) \ 2323 #define SIMD_UNOP_LIST(V) \
2324 V(Float32x4FromInt32x4, kArmFloat32x4FromInt32x4) \ 2324 V(F32x4SConvertI32x4, kArmF32x4SConvertI32x4) \
2325 V(Float32x4FromUint32x4, kArmFloat32x4FromUint32x4) \ 2325 V(F32x4UConvertI32x4, kArmF32x4UConvertI32x4) \
2326 V(Float32x4Abs, kArmFloat32x4Abs) \ 2326 V(F32x4Abs, kArmF32x4Abs) \
2327 V(Float32x4Neg, kArmFloat32x4Neg) \ 2327 V(F32x4Neg, kArmF32x4Neg) \
2328 V(Float32x4RecipApprox, kArmFloat32x4RecipApprox) \ 2328 V(F32x4RecipApprox, kArmF32x4RecipApprox) \
2329 V(Float32x4RecipSqrtApprox, kArmFloat32x4RecipSqrtApprox) \ 2329 V(F32x4RecipSqrtApprox, kArmF32x4RecipSqrtApprox) \
2330 V(Int32x4FromFloat32x4, kArmInt32x4FromFloat32x4) \ 2330 V(I32x4SConvertF32x4, kArmI32x4SConvertF32x4) \
2331 V(Uint32x4FromFloat32x4, kArmUint32x4FromFloat32x4) \ 2331 V(I32x4Neg, kArmI32x4Neg) \
2332 V(Int32x4Neg, kArmInt32x4Neg) \ 2332 V(I32x4UConvertF32x4, kArmI32x4UConvertF32x4) \
2333 V(Int16x8Neg, kArmInt16x8Neg) \ 2333 V(I16x8Neg, kArmI16x8Neg) \
2334 V(Int8x16Neg, kArmInt8x16Neg) \ 2334 V(I8x16Neg, kArmI8x16Neg) \
2335 V(Simd128Not, kArmSimd128Not) \ 2335 V(S128Not, kArmS128Not) \
2336 V(Simd1x4Not, kArmSimd128Not) \ 2336 V(S1x4Not, kArmS128Not) \
2337 V(Simd1x4AnyTrue, kArmSimd1x4AnyTrue) \ 2337 V(S1x4AnyTrue, kArmS1x4AnyTrue) \
2338 V(Simd1x4AllTrue, kArmSimd1x4AllTrue) \ 2338 V(S1x4AllTrue, kArmS1x4AllTrue) \
2339 V(Simd1x8Not, kArmSimd128Not) \ 2339 V(S1x8Not, kArmS128Not) \
2340 V(Simd1x8AnyTrue, kArmSimd1x8AnyTrue) \ 2340 V(S1x8AnyTrue, kArmS1x8AnyTrue) \
2341 V(Simd1x8AllTrue, kArmSimd1x8AllTrue) \ 2341 V(S1x8AllTrue, kArmS1x8AllTrue) \
2342 V(Simd1x16Not, kArmSimd128Not) \ 2342 V(S1x16Not, kArmS128Not) \
2343 V(Simd1x16AnyTrue, kArmSimd1x16AnyTrue) \ 2343 V(S1x16AnyTrue, kArmS1x16AnyTrue) \
2344 V(Simd1x16AllTrue, kArmSimd1x16AllTrue) 2344 V(S1x16AllTrue, kArmS1x16AllTrue)
2345 2345
2346 #define SIMD_BINOP_LIST(V) \ 2346 #define SIMD_SHIFT_OP_LIST(V) \
2347 V(Float32x4Add, kArmFloat32x4Add) \ 2347 V(I32x4Shl) \
2348 V(Float32x4Sub, kArmFloat32x4Sub) \ 2348 V(I32x4ShrS) \
2349 V(Float32x4Mul, kArmFloat32x4Mul) \ 2349 V(I32x4ShrU) \
2350 V(Float32x4Min, kArmFloat32x4Min) \ 2350 V(I16x8Shl) \
2351 V(Float32x4Max, kArmFloat32x4Max) \ 2351 V(I16x8ShrS) \
2352 V(Float32x4RecipRefine, kArmFloat32x4RecipRefine) \ 2352 V(I16x8ShrU) \
2353 V(Float32x4RecipSqrtRefine, kArmFloat32x4RecipSqrtRefine) \ 2353 V(I8x16Shl) \
2354 V(Float32x4Equal, kArmFloat32x4Equal) \ 2354 V(I8x16ShrS) \
2355 V(Float32x4NotEqual, kArmFloat32x4NotEqual) \ 2355 V(I8x16ShrU)
2356 V(Float32x4LessThan, kArmFloat32x4LessThan) \
2357 V(Float32x4LessThanOrEqual, kArmFloat32x4LessThanOrEqual) \
2358 V(Int32x4Add, kArmInt32x4Add) \
2359 V(Int32x4Sub, kArmInt32x4Sub) \
2360 V(Int32x4Mul, kArmInt32x4Mul) \
2361 V(Int32x4Min, kArmInt32x4Min) \
2362 V(Int32x4Max, kArmInt32x4Max) \
2363 V(Int32x4Equal, kArmInt32x4Equal) \
2364 V(Int32x4NotEqual, kArmInt32x4NotEqual) \
2365 V(Int32x4LessThan, kArmInt32x4LessThan) \
2366 V(Int32x4LessThanOrEqual, kArmInt32x4LessThanOrEqual) \
2367 V(Uint32x4Min, kArmUint32x4Min) \
2368 V(Uint32x4Max, kArmUint32x4Max) \
2369 V(Uint32x4LessThan, kArmUint32x4LessThan) \
2370 V(Uint32x4LessThanOrEqual, kArmUint32x4LessThanOrEqual) \
2371 V(Int16x8Add, kArmInt16x8Add) \
2372 V(Int16x8AddSaturate, kArmInt16x8AddSaturate) \
2373 V(Int16x8Sub, kArmInt16x8Sub) \
2374 V(Int16x8SubSaturate, kArmInt16x8SubSaturate) \
2375 V(Int16x8Mul, kArmInt16x8Mul) \
2376 V(Int16x8Min, kArmInt16x8Min) \
2377 V(Int16x8Max, kArmInt16x8Max) \
2378 V(Int16x8Equal, kArmInt16x8Equal) \
2379 V(Int16x8NotEqual, kArmInt16x8NotEqual) \
2380 V(Int16x8LessThan, kArmInt16x8LessThan) \
2381 V(Int16x8LessThanOrEqual, kArmInt16x8LessThanOrEqual) \
2382 V(Uint16x8AddSaturate, kArmUint16x8AddSaturate) \
2383 V(Uint16x8SubSaturate, kArmUint16x8SubSaturate) \
2384 V(Uint16x8Min, kArmUint16x8Min) \
2385 V(Uint16x8Max, kArmUint16x8Max) \
2386 V(Uint16x8LessThan, kArmUint16x8LessThan) \
2387 V(Uint16x8LessThanOrEqual, kArmUint16x8LessThanOrEqual) \
2388 V(Int8x16Add, kArmInt8x16Add) \
2389 V(Int8x16AddSaturate, kArmInt8x16AddSaturate) \
2390 V(Int8x16Sub, kArmInt8x16Sub) \
2391 V(Int8x16SubSaturate, kArmInt8x16SubSaturate) \
2392 V(Int8x16Mul, kArmInt8x16Mul) \
2393 V(Int8x16Min, kArmInt8x16Min) \
2394 V(Int8x16Max, kArmInt8x16Max) \
2395 V(Int8x16Equal, kArmInt8x16Equal) \
2396 V(Int8x16NotEqual, kArmInt8x16NotEqual) \
2397 V(Int8x16LessThan, kArmInt8x16LessThan) \
2398 V(Int8x16LessThanOrEqual, kArmInt8x16LessThanOrEqual) \
2399 V(Uint8x16AddSaturate, kArmUint8x16AddSaturate) \
2400 V(Uint8x16SubSaturate, kArmUint8x16SubSaturate) \
2401 V(Uint8x16Min, kArmUint8x16Min) \
2402 V(Uint8x16Max, kArmUint8x16Max) \
2403 V(Uint8x16LessThan, kArmUint8x16LessThan) \
2404 V(Uint8x16LessThanOrEqual, kArmUint8x16LessThanOrEqual) \
2405 V(Simd128And, kArmSimd128And) \
2406 V(Simd128Or, kArmSimd128Or) \
2407 V(Simd128Xor, kArmSimd128Xor) \
2408 V(Simd1x4And, kArmSimd128And) \
2409 V(Simd1x4Or, kArmSimd128Or) \
2410 V(Simd1x4Xor, kArmSimd128Xor) \
2411 V(Simd1x8And, kArmSimd128And) \
2412 V(Simd1x8Or, kArmSimd128Or) \
2413 V(Simd1x8Xor, kArmSimd128Xor) \
2414 V(Simd1x16And, kArmSimd128And) \
2415 V(Simd1x16Or, kArmSimd128Or) \
2416 V(Simd1x16Xor, kArmSimd128Xor)
2417 2356
2418 #define SIMD_SHIFT_OP_LIST(V) \ 2357 #define SIMD_BINOP_LIST(V) \
2419 V(Int32x4ShiftLeftByScalar) \ 2358 V(F32x4Add, kArmF32x4Add) \
2420 V(Int32x4ShiftRightByScalar) \ 2359 V(F32x4Sub, kArmF32x4Sub) \
2421 V(Uint32x4ShiftRightByScalar) \ 2360 V(F32x4Mul, kArmF32x4Mul) \
2422 V(Int16x8ShiftLeftByScalar) \ 2361 V(F32x4Min, kArmF32x4Min) \
2423 V(Int16x8ShiftRightByScalar) \ 2362 V(F32x4Max, kArmF32x4Max) \
2424 V(Uint16x8ShiftRightByScalar) \ 2363 V(F32x4RecipRefine, kArmF32x4RecipRefine) \
2425 V(Int8x16ShiftLeftByScalar) \ 2364 V(F32x4RecipSqrtRefine, kArmF32x4RecipSqrtRefine) \
2426 V(Int8x16ShiftRightByScalar) \ 2365 V(F32x4Eq, kArmF32x4Eq) \
2427 V(Uint8x16ShiftRightByScalar) 2366 V(F32x4Ne, kArmF32x4Ne) \
2367 V(F32x4Lt, kArmF32x4Lt) \
2368 V(F32x4Le, kArmF32x4Le) \
2369 V(I32x4Add, kArmI32x4Add) \
2370 V(I32x4Sub, kArmI32x4Sub) \
2371 V(I32x4Mul, kArmI32x4Mul) \
2372 V(I32x4MinS, kArmI32x4MinS) \
2373 V(I32x4MaxS, kArmI32x4MaxS) \
2374 V(I32x4Eq, kArmI32x4Eq) \
2375 V(I32x4Ne, kArmI32x4Ne) \
2376 V(I32x4LtS, kArmI32x4LtS) \
2377 V(I32x4LeS, kArmI32x4LeS) \
2378 V(I32x4MinU, kArmI32x4MinU) \
2379 V(I32x4MaxU, kArmI32x4MaxU) \
2380 V(I32x4LtU, kArmI32x4LtU) \
2381 V(I32x4LeU, kArmI32x4LeU) \
2382 V(I16x8Add, kArmI16x8Add) \
2383 V(I16x8AddSaturate, kArmI16x8AddSaturate) \
2384 V(I16x8Sub, kArmI16x8Sub) \
2385 V(I16x8SubSaturate, kArmI16x8SubSaturate) \
2386 V(I16x8Mul, kArmI16x8Mul) \
2387 V(I16x8MinS, kArmI16x8MinS) \
2388 V(I16x8MaxS, kArmI16x8MaxS) \
2389 V(I16x8Eq, kArmI16x8Eq) \
2390 V(I16x8Ne, kArmI16x8Ne) \
2391 V(I16x8LtS, kArmI16x8LtS) \
2392 V(I16x8LeS, kArmI16x8LeS) \
2393 V(I16x8AddSaturateU, kArmI16x8AddSaturateU) \
2394 V(I16x8SubSaturateU, kArmI16x8SubSaturateU) \
2395 V(I16x8MinU, kArmI16x8MinU) \
2396 V(I16x8MaxU, kArmI16x8MaxU) \
2397 V(I16x8LtU, kArmI16x8LtU) \
2398 V(I16x8LeU, kArmI16x8LeU) \
2399 V(I8x16Add, kArmI8x16Add) \
2400 V(I8x16AddSaturate, kArmI8x16AddSaturate) \
2401 V(I8x16Sub, kArmI8x16Sub) \
2402 V(I8x16SubSaturate, kArmI8x16SubSaturate) \
2403 V(I8x16Mul, kArmI8x16Mul) \
2404 V(I8x16MinS, kArmI8x16MinS) \
2405 V(I8x16MaxS, kArmI8x16MaxS) \
2406 V(I8x16Eq, kArmI8x16Eq) \
2407 V(I8x16Ne, kArmI8x16Ne) \
2408 V(I8x16LtS, kArmI8x16LtS) \
2409 V(I8x16LeS, kArmI8x16LeS) \
2410 V(I8x16AddSaturateU, kArmI8x16AddSaturateU) \
2411 V(I8x16SubSaturateU, kArmI8x16SubSaturateU) \
2412 V(I8x16MinU, kArmI8x16MinU) \
2413 V(I8x16MaxU, kArmI8x16MaxU) \
2414 V(I8x16LtU, kArmI8x16LtU) \
2415 V(I8x16LeU, kArmI8x16LeU) \
2416 V(S128And, kArmS128And) \
2417 V(S128Or, kArmS128Or) \
2418 V(S128Xor, kArmS128Xor) \
2419 V(S1x4And, kArmS128And) \
2420 V(S1x4Or, kArmS128Or) \
2421 V(S1x4Xor, kArmS128Xor) \
2422 V(S1x8And, kArmS128And) \
2423 V(S1x8Or, kArmS128Or) \
2424 V(S1x8Xor, kArmS128Xor) \
2425 V(S1x16And, kArmS128And) \
2426 V(S1x16Or, kArmS128Or) \
2427 V(S1x16Xor, kArmS128Xor)
2428 2428
2429 #define SIMD_VISIT_SPLAT(Type) \ 2429 #define SIMD_VISIT_SPLAT(Type) \
2430 void InstructionSelector::Visit##Type##Splat(Node* node) { \ 2430 void InstructionSelector::Visit##Type##Splat(Node* node) { \
2431 VisitRR(this, kArm##Type##Splat, node); \ 2431 VisitRR(this, kArm##Type##Splat, node); \
2432 } 2432 }
2433 SIMD_TYPE_LIST(SIMD_VISIT_SPLAT) 2433 SIMD_TYPE_LIST(SIMD_VISIT_SPLAT)
2434 #undef SIMD_VISIT_SPLAT 2434 #undef SIMD_VISIT_SPLAT
2435 2435
2436 #define SIMD_VISIT_EXTRACT_LANE(Type) \ 2436 #define SIMD_VISIT_EXTRACT_LANE(Type) \
2437 void InstructionSelector::Visit##Type##ExtractLane(Node* node) { \ 2437 void InstructionSelector::Visit##Type##ExtractLane(Node* node) { \
2438 VisitRRI(this, kArm##Type##ExtractLane, node); \ 2438 VisitRRI(this, kArm##Type##ExtractLane, node); \
2439 } 2439 }
2440 SIMD_TYPE_LIST(SIMD_VISIT_EXTRACT_LANE) 2440 SIMD_TYPE_LIST(SIMD_VISIT_EXTRACT_LANE)
2441 #undef SIMD_VISIT_EXTRACT_LANE 2441 #undef SIMD_VISIT_EXTRACT_LANE
2442 2442
2443 #define SIMD_VISIT_REPLACE_LANE(Type) \ 2443 #define SIMD_VISIT_REPLACE_LANE(Type) \
2444 void InstructionSelector::Visit##Type##ReplaceLane(Node* node) { \ 2444 void InstructionSelector::Visit##Type##ReplaceLane(Node* node) { \
2445 VisitRRIR(this, kArm##Type##ReplaceLane, node); \ 2445 VisitRRIR(this, kArm##Type##ReplaceLane, node); \
2446 } 2446 }
2447 SIMD_TYPE_LIST(SIMD_VISIT_REPLACE_LANE) 2447 SIMD_TYPE_LIST(SIMD_VISIT_REPLACE_LANE)
2448 #undef SIMD_VISIT_REPLACE_LANE 2448 #undef SIMD_VISIT_REPLACE_LANE
2449 2449
2450 #define SIMD_VISIT_ZERO_OP(Name) \ 2450 #define SIMD_VISIT_ZERO_OP(Name) \
2451 void InstructionSelector::Visit##Name(Node* node) { \ 2451 void InstructionSelector::Visit##Name(Node* node) { \
2452 ArmOperandGenerator g(this); \ 2452 ArmOperandGenerator g(this); \
2453 Emit(kArmSimd128Zero, g.DefineAsRegister(node), g.DefineAsRegister(node)); \ 2453 Emit(kArmS128Zero, g.DefineAsRegister(node), g.DefineAsRegister(node)); \
2454 } 2454 }
2455 SIMD_ZERO_OP_LIST(SIMD_VISIT_ZERO_OP) 2455 SIMD_ZERO_OP_LIST(SIMD_VISIT_ZERO_OP)
2456 #undef SIMD_VISIT_ZERO_OP 2456 #undef SIMD_VISIT_ZERO_OP
2457 2457
2458 #define SIMD_VISIT_UNOP(Name, instruction) \ 2458 #define SIMD_VISIT_UNOP(Name, instruction) \
2459 void InstructionSelector::Visit##Name(Node* node) { \ 2459 void InstructionSelector::Visit##Name(Node* node) { \
2460 VisitRR(this, instruction, node); \ 2460 VisitRR(this, instruction, node); \
2461 } 2461 }
2462 SIMD_UNOP_LIST(SIMD_VISIT_UNOP) 2462 SIMD_UNOP_LIST(SIMD_VISIT_UNOP)
2463 #undef SIMD_VISIT_UNOP 2463 #undef SIMD_VISIT_UNOP
2464 2464
2465 #define SIMD_VISIT_BINOP(Name, instruction) \
2466 void InstructionSelector::Visit##Name(Node* node) { \
2467 VisitRRR(this, instruction, node); \
2468 }
2469 SIMD_BINOP_LIST(SIMD_VISIT_BINOP)
2470 #undef SIMD_VISIT_BINOP
2471
2472 #define SIMD_VISIT_SHIFT_OP(Name) \ 2465 #define SIMD_VISIT_SHIFT_OP(Name) \
2473 void InstructionSelector::Visit##Name(Node* node) { \ 2466 void InstructionSelector::Visit##Name(Node* node) { \
2474 VisitRRI(this, kArm##Name, node); \ 2467 VisitRRI(this, kArm##Name, node); \
2475 } 2468 }
2476 SIMD_SHIFT_OP_LIST(SIMD_VISIT_SHIFT_OP) 2469 SIMD_SHIFT_OP_LIST(SIMD_VISIT_SHIFT_OP)
2477 #undef SIMD_VISIT_SHIFT_OP 2470 #undef SIMD_VISIT_SHIFT_OP
2478 2471
2479 #define SIMD_VISIT_SELECT_OP(format) \ 2472 #define SIMD_VISIT_BINOP(Name, instruction) \
2480 void InstructionSelector::VisitSimd##format##Select(Node* node) { \ 2473 void InstructionSelector::Visit##Name(Node* node) { \
2481 VisitRRRR(this, kArmSimd128Select, node); \ 2474 VisitRRR(this, instruction, node); \
2475 }
2476 SIMD_BINOP_LIST(SIMD_VISIT_BINOP)
2477 #undef SIMD_VISIT_BINOP
2478
2479 #define SIMD_VISIT_SELECT_OP(format) \
2480 void InstructionSelector::VisitS##format##Select(Node* node) { \
2481 VisitRRRR(this, kArmS128Select, node); \
2482 } 2482 }
2483 SIMD_FORMAT_LIST(SIMD_VISIT_SELECT_OP) 2483 SIMD_FORMAT_LIST(SIMD_VISIT_SELECT_OP)
2484 #undef SIMD_VISIT_SELECT_OP 2484 #undef SIMD_VISIT_SELECT_OP
2485 2485
2486 // static 2486 // static
2487 MachineOperatorBuilder::Flags 2487 MachineOperatorBuilder::Flags
2488 InstructionSelector::SupportedMachineOperatorFlags() { 2488 InstructionSelector::SupportedMachineOperatorFlags() {
2489 MachineOperatorBuilder::Flags flags; 2489 MachineOperatorBuilder::Flags flags;
2490 if (CpuFeatures::IsSupported(SUDIV)) { 2490 if (CpuFeatures::IsSupported(SUDIV)) {
2491 // The sdiv and udiv instructions correctly return 0 if the divisor is 0, 2491 // The sdiv and udiv instructions correctly return 0 if the divisor is 0,
(...skipping 24 matching lines...) Expand all
2516 Vector<MachineType> req_aligned = Vector<MachineType>::New(2); 2516 Vector<MachineType> req_aligned = Vector<MachineType>::New(2);
2517 req_aligned[0] = MachineType::Float32(); 2517 req_aligned[0] = MachineType::Float32();
2518 req_aligned[1] = MachineType::Float64(); 2518 req_aligned[1] = MachineType::Float64();
2519 return MachineOperatorBuilder::AlignmentRequirements:: 2519 return MachineOperatorBuilder::AlignmentRequirements::
2520 SomeUnalignedAccessUnsupported(req_aligned, req_aligned); 2520 SomeUnalignedAccessUnsupported(req_aligned, req_aligned);
2521 } 2521 }
2522 2522
2523 } // namespace compiler 2523 } // namespace compiler
2524 } // namespace internal 2524 } // namespace internal
2525 } // namespace v8 2525 } // namespace v8
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