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Side by Side Diff: src/compiler/arm/instruction-codes-arm.h

Issue 2776753004: [wasm] Make Opcode names consistent across architectures, implementations (Closed)
Patch Set: Scalar fix Created 3 years, 8 months ago
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« src/compiler/arm/code-generator-arm.cc ('K') | « src/compiler/arm/code-generator-arm.cc ('k') | src/compiler/arm/instruction-scheduler-arm.cc » ('j') | src/compiler/machine-operator.h » ('J')
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1 // Copyright 2014 the V8 project authors. All rights reserved. 1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ 5 #ifndef V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
6 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ 6 #define V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
7 7
8 namespace v8 { 8 namespace v8 {
9 namespace internal { 9 namespace internal {
10 namespace compiler { 10 namespace compiler {
(...skipping 106 matching lines...) Expand 10 before | Expand all | Expand 10 after
117 V(ArmLdrb) \ 117 V(ArmLdrb) \
118 V(ArmLdrsb) \ 118 V(ArmLdrsb) \
119 V(ArmStrb) \ 119 V(ArmStrb) \
120 V(ArmLdrh) \ 120 V(ArmLdrh) \
121 V(ArmLdrsh) \ 121 V(ArmLdrsh) \
122 V(ArmStrh) \ 122 V(ArmStrh) \
123 V(ArmLdr) \ 123 V(ArmLdr) \
124 V(ArmStr) \ 124 V(ArmStr) \
125 V(ArmPush) \ 125 V(ArmPush) \
126 V(ArmPoke) \ 126 V(ArmPoke) \
127 V(ArmFloat32x4Splat) \ 127 V(ArmF32x4Splat) \
128 V(ArmFloat32x4ExtractLane) \ 128 V(ArmF32x4ExtractLane) \
129 V(ArmFloat32x4ReplaceLane) \ 129 V(ArmF32x4ReplaceLane) \
130 V(ArmFloat32x4FromInt32x4) \ 130 V(ArmF32x4Abs) \
131 V(ArmFloat32x4FromUint32x4) \ 131 V(ArmF32x4Neg) \
132 V(ArmFloat32x4Abs) \ 132 V(ArmF32x4RecipApprox) \
133 V(ArmFloat32x4Neg) \ 133 V(ArmF32x4RecipSqrtApprox) \
134 V(ArmFloat32x4RecipApprox) \ 134 V(ArmF32x4Add) \
135 V(ArmFloat32x4RecipSqrtApprox) \ 135 V(ArmF32x4Sub) \
136 V(ArmFloat32x4Add) \ 136 V(ArmF32x4Mul) \
137 V(ArmFloat32x4Sub) \ 137 V(ArmF32x4Min) \
138 V(ArmFloat32x4Mul) \ 138 V(ArmF32x4Max) \
139 V(ArmFloat32x4Min) \ 139 V(ArmF32x4RecipRefine) \
140 V(ArmFloat32x4Max) \ 140 V(ArmF32x4RecipSqrtRefine) \
141 V(ArmFloat32x4RecipRefine) \ 141 V(ArmF32x4Eq) \
142 V(ArmFloat32x4RecipSqrtRefine) \ 142 V(ArmF32x4Ne) \
143 V(ArmFloat32x4Equal) \ 143 V(ArmF32x4Lt) \
144 V(ArmFloat32x4NotEqual) \ 144 V(ArmF32x4Le) \
145 V(ArmFloat32x4LessThan) \ 145 V(ArmF32x4SConvertI32x4) \
146 V(ArmFloat32x4LessThanOrEqual) \ 146 V(ArmF32x4UConvertI32x4) \
147 V(ArmInt32x4Splat) \ 147 V(ArmI32x4Splat) \
148 V(ArmInt32x4ExtractLane) \ 148 V(ArmI32x4ExtractLane) \
149 V(ArmInt32x4ReplaceLane) \ 149 V(ArmI32x4ReplaceLane) \
150 V(ArmInt32x4FromFloat32x4) \ 150 V(ArmI32x4Neg) \
151 V(ArmUint32x4FromFloat32x4) \ 151 V(ArmI32x4Add) \
152 V(ArmInt32x4Neg) \ 152 V(ArmI32x4Sub) \
153 V(ArmInt32x4ShiftLeftByScalar) \ 153 V(ArmI32x4Mul) \
154 V(ArmInt32x4ShiftRightByScalar) \ 154 V(ArmI32x4MinS) \
155 V(ArmInt32x4Add) \ 155 V(ArmI32x4MaxS) \
156 V(ArmInt32x4Sub) \ 156 V(ArmI32x4Shl) \
157 V(ArmInt32x4Mul) \ 157 V(ArmI32x4ShrS) \
158 V(ArmInt32x4Min) \ 158 V(ArmI32x4Eq) \
159 V(ArmInt32x4Max) \ 159 V(ArmI32x4Ne) \
160 V(ArmInt32x4Equal) \ 160 V(ArmI32x4LtS) \
161 V(ArmInt32x4NotEqual) \ 161 V(ArmI32x4LeS) \
162 V(ArmInt32x4LessThan) \ 162 V(ArmI32x4SConvertF32x4) \
163 V(ArmInt32x4LessThanOrEqual) \ 163 V(ArmI32x4MinU) \
164 V(ArmUint32x4ShiftRightByScalar) \ 164 V(ArmI32x4MaxU) \
165 V(ArmUint32x4Min) \ 165 V(ArmI32x4ShrU) \
166 V(ArmUint32x4Max) \ 166 V(ArmI32x4LtU) \
167 V(ArmUint32x4LessThan) \ 167 V(ArmI32x4LeU) \
168 V(ArmUint32x4LessThanOrEqual) \ 168 V(ArmI32x4UConvertF32x4) \
169 V(ArmInt16x8Splat) \ 169 V(ArmI16x8Splat) \
170 V(ArmInt16x8ExtractLane) \ 170 V(ArmI16x8ExtractLane) \
171 V(ArmInt16x8ReplaceLane) \ 171 V(ArmI16x8ReplaceLane) \
172 V(ArmInt16x8Neg) \ 172 V(ArmI16x8Neg) \
173 V(ArmInt16x8ShiftLeftByScalar) \ 173 V(ArmI16x8Add) \
174 V(ArmInt16x8ShiftRightByScalar) \ 174 V(ArmI16x8AddSaturate) \
175 V(ArmInt16x8Add) \ 175 V(ArmI16x8Sub) \
176 V(ArmInt16x8AddSaturate) \ 176 V(ArmI16x8SubSaturate) \
177 V(ArmInt16x8Sub) \ 177 V(ArmI16x8Mul) \
178 V(ArmInt16x8SubSaturate) \ 178 V(ArmI16x8MinS) \
179 V(ArmInt16x8Mul) \ 179 V(ArmI16x8MaxS) \
180 V(ArmInt16x8Min) \ 180 V(ArmI16x8Shl) \
181 V(ArmInt16x8Max) \ 181 V(ArmI16x8ShrS) \
182 V(ArmInt16x8Equal) \ 182 V(ArmI16x8Eq) \
183 V(ArmInt16x8NotEqual) \ 183 V(ArmI16x8Ne) \
184 V(ArmInt16x8LessThan) \ 184 V(ArmI16x8LtS) \
185 V(ArmInt16x8LessThanOrEqual) \ 185 V(ArmI16x8LeS) \
186 V(ArmUint16x8ShiftRightByScalar) \ 186 V(ArmI16x8AddSaturateU) \
187 V(ArmUint16x8AddSaturate) \ 187 V(ArmI16x8SubSaturateU) \
188 V(ArmUint16x8SubSaturate) \ 188 V(ArmI16x8MinU) \
189 V(ArmUint16x8Min) \ 189 V(ArmI16x8MaxU) \
190 V(ArmUint16x8Max) \ 190 V(ArmI16x8ShrU) \
191 V(ArmUint16x8LessThan) \ 191 V(ArmI16x8LtU) \
192 V(ArmUint16x8LessThanOrEqual) \ 192 V(ArmI16x8LeU) \
193 V(ArmInt8x16Splat) \ 193 V(ArmI8x16Splat) \
194 V(ArmInt8x16ExtractLane) \ 194 V(ArmI8x16ExtractLane) \
195 V(ArmInt8x16ReplaceLane) \ 195 V(ArmI8x16ReplaceLane) \
196 V(ArmInt8x16Neg) \ 196 V(ArmI8x16Neg) \
197 V(ArmInt8x16ShiftLeftByScalar) \ 197 V(ArmI8x16Add) \
198 V(ArmInt8x16ShiftRightByScalar) \ 198 V(ArmI8x16AddSaturate) \
199 V(ArmInt8x16Add) \ 199 V(ArmI8x16Sub) \
200 V(ArmInt8x16AddSaturate) \ 200 V(ArmI8x16SubSaturate) \
201 V(ArmInt8x16Sub) \ 201 V(ArmI8x16Mul) \
202 V(ArmInt8x16SubSaturate) \ 202 V(ArmI8x16MinS) \
203 V(ArmInt8x16Mul) \ 203 V(ArmI8x16MaxS) \
204 V(ArmInt8x16Min) \ 204 V(ArmI8x16Shl) \
205 V(ArmInt8x16Max) \ 205 V(ArmI8x16ShrS) \
206 V(ArmInt8x16Equal) \ 206 V(ArmI8x16Eq) \
207 V(ArmInt8x16NotEqual) \ 207 V(ArmI8x16Ne) \
208 V(ArmInt8x16LessThan) \ 208 V(ArmI8x16LtS) \
209 V(ArmInt8x16LessThanOrEqual) \ 209 V(ArmI8x16LeS) \
210 V(ArmUint8x16ShiftRightByScalar) \ 210 V(ArmI8x16AddSaturateU) \
211 V(ArmUint8x16AddSaturate) \ 211 V(ArmI8x16SubSaturateU) \
212 V(ArmUint8x16SubSaturate) \ 212 V(ArmI8x16MinU) \
213 V(ArmUint8x16Min) \ 213 V(ArmI8x16MaxU) \
214 V(ArmUint8x16Max) \ 214 V(ArmI8x16LtU) \
215 V(ArmUint8x16LessThan) \ 215 V(ArmI8x16LeU) \
216 V(ArmUint8x16LessThanOrEqual) \ 216 V(ArmI8x16ShrU) \
217 V(ArmSimd128Zero) \ 217 V(ArmS128Zero) \
218 V(ArmSimd128And) \ 218 V(ArmS128And) \
219 V(ArmSimd128Or) \ 219 V(ArmS128Or) \
220 V(ArmSimd128Xor) \ 220 V(ArmS128Xor) \
221 V(ArmSimd128Not) \ 221 V(ArmS128Not) \
222 V(ArmSimd128Select) \ 222 V(ArmSimd128Select) \
bbudge 2017/03/28 00:13:26 Simd -> S
gdeepti 2017/03/28 22:06:40 Done.
223 V(ArmSimd1x4AnyTrue) \ 223 V(ArmS1x4AnyTrue) \
224 V(ArmSimd1x4AllTrue) \ 224 V(ArmS1x4AllTrue) \
225 V(ArmSimd1x8AnyTrue) \ 225 V(ArmS1x8AnyTrue) \
226 V(ArmSimd1x8AllTrue) \ 226 V(ArmS1x8AllTrue) \
227 V(ArmSimd1x16AnyTrue) \ 227 V(ArmS1x16AnyTrue) \
228 V(ArmSimd1x16AllTrue) 228 V(ArmS1x16AllTrue)
229 229
230 // Addressing modes represent the "shape" of inputs to an instruction. 230 // Addressing modes represent the "shape" of inputs to an instruction.
231 // Many instructions support multiple addressing modes. Addressing modes 231 // Many instructions support multiple addressing modes. Addressing modes
232 // are encoded into the InstructionCode of the instruction and tell the 232 // are encoded into the InstructionCode of the instruction and tell the
233 // code generator after register allocation which assembler method to call. 233 // code generator after register allocation which assembler method to call.
234 #define TARGET_ADDRESSING_MODE_LIST(V) \ 234 #define TARGET_ADDRESSING_MODE_LIST(V) \
235 V(Offset_RI) /* [%r0 + K] */ \ 235 V(Offset_RI) /* [%r0 + K] */ \
236 V(Offset_RR) /* [%r0 + %r1] */ \ 236 V(Offset_RR) /* [%r0 + %r1] */ \
237 V(Operand2_I) /* K */ \ 237 V(Operand2_I) /* K */ \
238 V(Operand2_R) /* %r0 */ \ 238 V(Operand2_R) /* %r0 */ \
239 V(Operand2_R_ASR_I) /* %r0 ASR K */ \ 239 V(Operand2_R_ASR_I) /* %r0 ASR K */ \
240 V(Operand2_R_LSL_I) /* %r0 LSL K */ \ 240 V(Operand2_R_LSL_I) /* %r0 LSL K */ \
241 V(Operand2_R_LSR_I) /* %r0 LSR K */ \ 241 V(Operand2_R_LSR_I) /* %r0 LSR K */ \
242 V(Operand2_R_ROR_I) /* %r0 ROR K */ \ 242 V(Operand2_R_ROR_I) /* %r0 ROR K */ \
243 V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \ 243 V(Operand2_R_ASR_R) /* %r0 ASR %r1 */ \
244 V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \ 244 V(Operand2_R_LSL_R) /* %r0 LSL %r1 */ \
245 V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \ 245 V(Operand2_R_LSR_R) /* %r0 LSR %r1 */ \
246 V(Operand2_R_ROR_R) /* %r0 ROR %r1 */ 246 V(Operand2_R_ROR_R) /* %r0 ROR %r1 */
247 247
248 } // namespace compiler 248 } // namespace compiler
249 } // namespace internal 249 } // namespace internal
250 } // namespace v8 250 } // namespace v8
251 251
252 #endif // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_ 252 #endif // V8_COMPILER_ARM_INSTRUCTION_CODES_ARM_H_
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« src/compiler/arm/code-generator-arm.cc ('K') | « src/compiler/arm/code-generator-arm.cc ('k') | src/compiler/arm/instruction-scheduler-arm.cc » ('j') | src/compiler/machine-operator.h » ('J')

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