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1 // Copyright 2014 the V8 project authors. All rights reserved. | 1 // Copyright 2014 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 #include "src/compiler/code-generator.h" | 5 #include "src/compiler/code-generator.h" |
6 | 6 |
7 #include "src/arm/macro-assembler-arm.h" | 7 #include "src/arm/macro-assembler-arm.h" |
8 #include "src/assembler-inl.h" | 8 #include "src/assembler-inl.h" |
9 #include "src/compilation-info.h" | 9 #include "src/compilation-info.h" |
10 #include "src/compiler/code-generator-impl.h" | 10 #include "src/compiler/code-generator-impl.h" |
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1549 frame_access_state()->IncreaseSPDelta(1); | 1549 frame_access_state()->IncreaseSPDelta(1); |
1550 } | 1550 } |
1551 DCHECK_EQ(LeaveCC, i.OutputSBit()); | 1551 DCHECK_EQ(LeaveCC, i.OutputSBit()); |
1552 break; | 1552 break; |
1553 case kArmPoke: { | 1553 case kArmPoke: { |
1554 int const slot = MiscField::decode(instr->opcode()); | 1554 int const slot = MiscField::decode(instr->opcode()); |
1555 __ str(i.InputRegister(0), MemOperand(sp, slot * kPointerSize)); | 1555 __ str(i.InputRegister(0), MemOperand(sp, slot * kPointerSize)); |
1556 DCHECK_EQ(LeaveCC, i.OutputSBit()); | 1556 DCHECK_EQ(LeaveCC, i.OutputSBit()); |
1557 break; | 1557 break; |
1558 } | 1558 } |
1559 case kArmFloat32x4Splat: { | 1559 case kArmF32x4Splat: { |
1560 __ vdup(i.OutputSimd128Register(), i.InputFloatRegister(0)); | 1560 __ vdup(i.OutputSimd128Register(), i.InputFloatRegister(0)); |
1561 break; | 1561 break; |
1562 } | 1562 } |
1563 case kArmFloat32x4ExtractLane: { | 1563 case kArmF32x4ExtractLane: { |
1564 __ ExtractLane(i.OutputFloatRegister(), i.InputSimd128Register(0), | 1564 __ ExtractLane(i.OutputFloatRegister(), i.InputSimd128Register(0), |
1565 kScratchReg, i.InputInt8(1)); | 1565 kScratchReg, i.InputInt8(1)); |
1566 break; | 1566 break; |
1567 } | 1567 } |
1568 case kArmFloat32x4ReplaceLane: { | 1568 case kArmF32x4ReplaceLane: { |
1569 __ ReplaceLane(i.OutputSimd128Register(), i.InputSimd128Register(0), | 1569 __ ReplaceLane(i.OutputSimd128Register(), i.InputSimd128Register(0), |
1570 i.InputFloatRegister(2), kScratchReg, i.InputInt8(1)); | 1570 i.InputFloatRegister(2), kScratchReg, i.InputInt8(1)); |
1571 break; | 1571 break; |
1572 } | 1572 } |
1573 case kArmFloat32x4FromInt32x4: { | 1573 case kArmF32x4Abs: { |
1574 __ vcvt_f32_s32(i.OutputSimd128Register(), i.InputSimd128Register(0)); | |
1575 break; | |
1576 } | |
1577 case kArmFloat32x4FromUint32x4: { | |
1578 __ vcvt_f32_u32(i.OutputSimd128Register(), i.InputSimd128Register(0)); | |
1579 break; | |
1580 } | |
1581 case kArmFloat32x4Abs: { | |
1582 __ vabs(i.OutputSimd128Register(), i.InputSimd128Register(0)); | 1574 __ vabs(i.OutputSimd128Register(), i.InputSimd128Register(0)); |
1583 break; | 1575 break; |
1584 } | 1576 } |
1585 case kArmFloat32x4Neg: { | 1577 case kArmF32x4Neg: { |
1586 __ vneg(i.OutputSimd128Register(), i.InputSimd128Register(0)); | 1578 __ vneg(i.OutputSimd128Register(), i.InputSimd128Register(0)); |
1587 break; | 1579 break; |
1588 } | 1580 } |
1589 case kArmFloat32x4RecipApprox: { | 1581 case kArmF32x4RecipApprox: { |
1590 __ vrecpe(i.OutputSimd128Register(), i.InputSimd128Register(0)); | 1582 __ vrecpe(i.OutputSimd128Register(), i.InputSimd128Register(0)); |
1591 break; | 1583 break; |
1592 } | 1584 } |
1593 case kArmFloat32x4RecipSqrtApprox: { | 1585 case kArmF32x4RecipSqrtApprox: { |
1594 __ vrsqrte(i.OutputSimd128Register(), i.InputSimd128Register(0)); | 1586 __ vrsqrte(i.OutputSimd128Register(), i.InputSimd128Register(0)); |
1595 break; | 1587 break; |
1596 } | 1588 } |
1597 case kArmFloat32x4Add: { | 1589 case kArmF32x4Add: { |
1598 __ vadd(i.OutputSimd128Register(), i.InputSimd128Register(0), | 1590 __ vadd(i.OutputSimd128Register(), i.InputSimd128Register(0), |
1599 i.InputSimd128Register(1)); | 1591 i.InputSimd128Register(1)); |
1600 break; | 1592 break; |
1601 } | 1593 } |
1602 case kArmFloat32x4Sub: { | 1594 case kArmF32x4Sub: { |
1603 __ vsub(i.OutputSimd128Register(), i.InputSimd128Register(0), | 1595 __ vsub(i.OutputSimd128Register(), i.InputSimd128Register(0), |
1604 i.InputSimd128Register(1)); | 1596 i.InputSimd128Register(1)); |
1605 break; | 1597 break; |
1606 } | 1598 } |
1607 case kArmFloat32x4Mul: { | 1599 case kArmF32x4Mul: { |
1608 __ vmul(i.OutputSimd128Register(), i.InputSimd128Register(0), | 1600 __ vmul(i.OutputSimd128Register(), i.InputSimd128Register(0), |
1609 i.InputSimd128Register(1)); | 1601 i.InputSimd128Register(1)); |
1610 break; | 1602 break; |
1611 } | 1603 } |
1612 case kArmFloat32x4Min: { | 1604 case kArmF32x4Min: { |
1613 __ vmin(i.OutputSimd128Register(), i.InputSimd128Register(0), | 1605 __ vmin(i.OutputSimd128Register(), i.InputSimd128Register(0), |
1614 i.InputSimd128Register(1)); | 1606 i.InputSimd128Register(1)); |
1615 break; | 1607 break; |
1616 } | 1608 } |
1617 case kArmFloat32x4Max: { | 1609 case kArmF32x4Max: { |
1618 __ vmax(i.OutputSimd128Register(), i.InputSimd128Register(0), | 1610 __ vmax(i.OutputSimd128Register(), i.InputSimd128Register(0), |
1619 i.InputSimd128Register(1)); | 1611 i.InputSimd128Register(1)); |
1620 break; | 1612 break; |
1621 } | 1613 } |
1622 case kArmFloat32x4RecipRefine: { | 1614 case kArmF32x4RecipRefine: { |
1623 __ vrecps(i.OutputSimd128Register(), i.InputSimd128Register(0), | 1615 __ vrecps(i.OutputSimd128Register(), i.InputSimd128Register(0), |
1624 i.InputSimd128Register(1)); | 1616 i.InputSimd128Register(1)); |
1625 break; | 1617 break; |
1626 } | 1618 } |
1627 case kArmFloat32x4RecipSqrtRefine: { | 1619 case kArmF32x4RecipSqrtRefine: { |
1628 __ vrsqrts(i.OutputSimd128Register(), i.InputSimd128Register(0), | 1620 __ vrsqrts(i.OutputSimd128Register(), i.InputSimd128Register(0), |
1629 i.InputSimd128Register(1)); | 1621 i.InputSimd128Register(1)); |
1630 break; | 1622 break; |
1631 } | 1623 } |
1632 case kArmFloat32x4Equal: { | 1624 case kArmF32x4Eq: { |
1633 __ vceq(i.OutputSimd128Register(), i.InputSimd128Register(0), | 1625 __ vceq(i.OutputSimd128Register(), i.InputSimd128Register(0), |
1634 i.InputSimd128Register(1)); | 1626 i.InputSimd128Register(1)); |
1635 break; | 1627 break; |
1636 } | 1628 } |
1637 case kArmFloat32x4NotEqual: { | 1629 case kArmF32x4Ne: { |
1638 Simd128Register dst = i.OutputSimd128Register(); | 1630 Simd128Register dst = i.OutputSimd128Register(); |
1639 __ vceq(dst, i.InputSimd128Register(0), i.InputSimd128Register(1)); | 1631 __ vceq(dst, i.InputSimd128Register(0), i.InputSimd128Register(1)); |
1640 __ vmvn(dst, dst); | 1632 __ vmvn(dst, dst); |
1641 break; | 1633 break; |
1642 } | 1634 } |
1643 case kArmFloat32x4LessThan: { | 1635 case kArmF32x4Lt: { |
1644 __ vcgt(i.OutputSimd128Register(), i.InputSimd128Register(1), | 1636 __ vcgt(i.OutputSimd128Register(), i.InputSimd128Register(1), |
1645 i.InputSimd128Register(0)); | 1637 i.InputSimd128Register(0)); |
1646 break; | 1638 break; |
1647 } | 1639 } |
1648 case kArmFloat32x4LessThanOrEqual: { | 1640 case kArmF32x4Le: { |
1649 __ vcge(i.OutputSimd128Register(), i.InputSimd128Register(1), | 1641 __ vcge(i.OutputSimd128Register(), i.InputSimd128Register(1), |
1650 i.InputSimd128Register(0)); | 1642 i.InputSimd128Register(0)); |
1651 break; | 1643 break; |
1652 } | 1644 } |
1653 case kArmInt32x4Splat: { | 1645 case kArmF32x4SConvertI32x4: { |
bbudge
2017/03/28 00:13:26
these are unary ops, so should remain above.
gdeepti
2017/03/28 22:06:40
Done.
| |
1646 __ vcvt_f32_s32(i.OutputSimd128Register(), i.InputSimd128Register(0)); | |
1647 break; | |
1648 } | |
1649 case kArmF32x4UConvertI32x4: { | |
1650 __ vcvt_f32_u32(i.OutputSimd128Register(), i.InputSimd128Register(0)); | |
1651 break; | |
1652 } | |
1653 case kArmI32x4Splat: { | |
1654 __ vdup(Neon32, i.OutputSimd128Register(), i.InputRegister(0)); | 1654 __ vdup(Neon32, i.OutputSimd128Register(), i.InputRegister(0)); |
1655 break; | 1655 break; |
1656 } | 1656 } |
1657 case kArmInt32x4ExtractLane: { | 1657 case kArmI32x4ExtractLane: { |
1658 __ ExtractLane(i.OutputRegister(), i.InputSimd128Register(0), NeonS32, | 1658 __ ExtractLane(i.OutputRegister(), i.InputSimd128Register(0), NeonS32, |
1659 i.InputInt8(1)); | 1659 i.InputInt8(1)); |
1660 break; | 1660 break; |
1661 } | 1661 } |
1662 case kArmInt32x4ReplaceLane: { | 1662 case kArmI32x4ReplaceLane: { |
1663 __ ReplaceLane(i.OutputSimd128Register(), i.InputSimd128Register(0), | 1663 __ ReplaceLane(i.OutputSimd128Register(), i.InputSimd128Register(0), |
1664 i.InputRegister(2), NeonS32, i.InputInt8(1)); | 1664 i.InputRegister(2), NeonS32, i.InputInt8(1)); |
1665 break; | 1665 break; |
1666 } | 1666 } |
1667 case kArmInt32x4FromFloat32x4: { | 1667 case kArmI32x4Neg: { |
1668 __ vcvt_s32_f32(i.OutputSimd128Register(), i.InputSimd128Register(0)); | |
1669 break; | |
1670 } | |
1671 case kArmUint32x4FromFloat32x4: { | |
1672 __ vcvt_u32_f32(i.OutputSimd128Register(), i.InputSimd128Register(0)); | |
1673 break; | |
1674 } | |
1675 case kArmInt32x4Neg: { | |
1676 __ vneg(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0)); | 1668 __ vneg(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0)); |
1677 break; | 1669 break; |
1678 } | 1670 } |
1679 case kArmInt32x4ShiftLeftByScalar: { | 1671 case kArmI32x4Add: { |
1672 __ vadd(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1673 i.InputSimd128Register(1)); | |
1674 break; | |
1675 } | |
1676 case kArmI32x4Sub: { | |
1677 __ vsub(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1678 i.InputSimd128Register(1)); | |
1679 break; | |
1680 } | |
1681 case kArmI32x4Mul: { | |
1682 __ vmul(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1683 i.InputSimd128Register(1)); | |
1684 break; | |
1685 } | |
1686 case kArmI32x4MinS: { | |
1687 __ vmin(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1688 i.InputSimd128Register(1)); | |
1689 break; | |
1690 } | |
1691 case kArmI32x4MaxS: { | |
1692 __ vmax(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1693 i.InputSimd128Register(1)); | |
1694 break; | |
1695 } | |
1696 case kArmI32x4Shl: { | |
bbudge
2017/03/28 00:13:26
Shifts are unary and should be moved back.
gdeepti
2017/03/28 22:06:40
Done.
| |
1680 __ vshl(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0), | 1697 __ vshl(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1681 i.InputInt5(1)); | 1698 i.InputInt5(1)); |
1682 break; | 1699 break; |
1683 } | 1700 } |
1684 case kArmInt32x4ShiftRightByScalar: { | 1701 case kArmI32x4ShrS: { |
1685 __ vshr(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0), | 1702 __ vshr(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1686 i.InputInt5(1)); | 1703 i.InputInt5(1)); |
1687 break; | 1704 break; |
1688 } | 1705 } |
1689 case kArmInt32x4Add: { | 1706 case kArmI32x4Eq: { |
1690 __ vadd(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1691 i.InputSimd128Register(1)); | |
1692 break; | |
1693 } | |
1694 case kArmInt32x4Sub: { | |
1695 __ vsub(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1696 i.InputSimd128Register(1)); | |
1697 break; | |
1698 } | |
1699 case kArmInt32x4Mul: { | |
1700 __ vmul(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1701 i.InputSimd128Register(1)); | |
1702 break; | |
1703 } | |
1704 case kArmInt32x4Min: { | |
1705 __ vmin(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1706 i.InputSimd128Register(1)); | |
1707 break; | |
1708 } | |
1709 case kArmInt32x4Max: { | |
1710 __ vmax(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1711 i.InputSimd128Register(1)); | |
1712 break; | |
1713 } | |
1714 case kArmInt32x4Equal: { | |
1715 __ vceq(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0), | 1707 __ vceq(Neon32, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1716 i.InputSimd128Register(1)); | 1708 i.InputSimd128Register(1)); |
1717 break; | 1709 break; |
1718 } | 1710 } |
1719 case kArmInt32x4NotEqual: { | 1711 case kArmI32x4Ne: { |
1720 Simd128Register dst = i.OutputSimd128Register(); | 1712 Simd128Register dst = i.OutputSimd128Register(); |
1721 __ vceq(Neon32, dst, i.InputSimd128Register(0), | 1713 __ vceq(Neon32, dst, i.InputSimd128Register(0), |
1722 i.InputSimd128Register(1)); | 1714 i.InputSimd128Register(1)); |
1723 __ vmvn(dst, dst); | 1715 __ vmvn(dst, dst); |
1724 break; | 1716 break; |
1725 } | 1717 } |
1726 case kArmInt32x4LessThan: { | 1718 case kArmI32x4LtS: { |
1727 __ vcgt(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(1), | 1719 __ vcgt(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(1), |
1728 i.InputSimd128Register(0)); | 1720 i.InputSimd128Register(0)); |
1729 break; | 1721 break; |
1730 } | 1722 } |
1731 case kArmInt32x4LessThanOrEqual: { | 1723 case kArmI32x4LeS: { |
1732 __ vcge(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(1), | 1724 __ vcge(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(1), |
1733 i.InputSimd128Register(0)); | 1725 i.InputSimd128Register(0)); |
1734 break; | 1726 break; |
1735 } | 1727 } |
1736 case kArmUint32x4ShiftRightByScalar: { | 1728 case kArmI32x4SConvertF32x4: { |
1729 __ vcvt_s32_f32(i.OutputSimd128Register(), i.InputSimd128Register(0)); | |
1730 break; | |
1731 } | |
1732 case kArmI32x4MinU: { | |
1733 __ vmin(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1734 i.InputSimd128Register(1)); | |
1735 break; | |
1736 } | |
1737 case kArmI32x4MaxU: { | |
1738 __ vmax(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1739 i.InputSimd128Register(1)); | |
1740 break; | |
1741 } | |
1742 case kArmI32x4ShrU: { | |
1737 __ vshr(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(0), | 1743 __ vshr(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1738 i.InputInt5(1)); | 1744 i.InputInt5(1)); |
1739 break; | 1745 break; |
1740 } | 1746 } |
1741 case kArmUint32x4Min: { | 1747 case kArmI32x4LtU: { |
1742 __ vmin(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1743 i.InputSimd128Register(1)); | |
1744 break; | |
1745 } | |
1746 case kArmUint32x4Max: { | |
1747 __ vmax(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1748 i.InputSimd128Register(1)); | |
1749 break; | |
1750 } | |
1751 case kArmUint32x4LessThan: { | |
1752 __ vcgt(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(1), | 1748 __ vcgt(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(1), |
1753 i.InputSimd128Register(0)); | 1749 i.InputSimd128Register(0)); |
1754 break; | 1750 break; |
1755 } | 1751 } |
1756 case kArmUint32x4LessThanOrEqual: { | 1752 case kArmI32x4LeU: { |
1757 __ vcge(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(1), | 1753 __ vcge(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(1), |
1758 i.InputSimd128Register(0)); | 1754 i.InputSimd128Register(0)); |
1759 break; | 1755 break; |
1760 } | 1756 } |
1761 case kArmInt16x8Splat: { | 1757 case kArmI32x4UConvertF32x4: { |
1758 __ vcvt_u32_f32(i.OutputSimd128Register(), i.InputSimd128Register(0)); | |
1759 break; | |
1760 } | |
1761 case kArmI16x8Splat: { | |
1762 __ vdup(Neon16, i.OutputSimd128Register(), i.InputRegister(0)); | 1762 __ vdup(Neon16, i.OutputSimd128Register(), i.InputRegister(0)); |
1763 break; | 1763 break; |
1764 } | 1764 } |
1765 case kArmInt16x8ExtractLane: { | 1765 case kArmI16x8ExtractLane: { |
1766 __ ExtractLane(i.OutputRegister(), i.InputSimd128Register(0), NeonS16, | 1766 __ ExtractLane(i.OutputRegister(), i.InputSimd128Register(0), NeonS16, |
1767 i.InputInt8(1)); | 1767 i.InputInt8(1)); |
1768 break; | 1768 break; |
1769 } | 1769 } |
1770 case kArmInt16x8ReplaceLane: { | 1770 case kArmI16x8ReplaceLane: { |
1771 __ ReplaceLane(i.OutputSimd128Register(), i.InputSimd128Register(0), | 1771 __ ReplaceLane(i.OutputSimd128Register(), i.InputSimd128Register(0), |
1772 i.InputRegister(2), NeonS16, i.InputInt8(1)); | 1772 i.InputRegister(2), NeonS16, i.InputInt8(1)); |
1773 break; | 1773 break; |
1774 } | 1774 } |
1775 case kArmInt16x8Neg: { | 1775 case kArmI16x8Neg: { |
1776 __ vneg(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0)); | 1776 __ vneg(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0)); |
1777 break; | 1777 break; |
1778 } | 1778 } |
1779 case kArmInt16x8ShiftLeftByScalar: { | 1779 case kArmI16x8Add: { |
1780 __ vadd(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1781 i.InputSimd128Register(1)); | |
1782 break; | |
1783 } | |
1784 case kArmI16x8AddSaturate: { | |
1785 __ vqadd(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1786 i.InputSimd128Register(1)); | |
1787 break; | |
1788 } | |
1789 case kArmI16x8Sub: { | |
1790 __ vsub(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1791 i.InputSimd128Register(1)); | |
1792 break; | |
1793 } | |
1794 case kArmI16x8SubSaturate: { | |
1795 __ vqsub(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1796 i.InputSimd128Register(1)); | |
1797 break; | |
1798 } | |
1799 case kArmI16x8Mul: { | |
1800 __ vmul(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1801 i.InputSimd128Register(1)); | |
1802 break; | |
1803 } | |
1804 case kArmI16x8MinS: { | |
1805 __ vmin(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1806 i.InputSimd128Register(1)); | |
1807 break; | |
1808 } | |
1809 case kArmI16x8MaxS: { | |
1810 __ vmax(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1811 i.InputSimd128Register(1)); | |
1812 break; | |
1813 } | |
1814 case kArmI16x8Shl: { | |
1780 __ vshl(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0), | 1815 __ vshl(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1781 i.InputInt4(1)); | 1816 i.InputInt4(1)); |
1782 break; | 1817 break; |
1783 } | 1818 } |
1784 case kArmInt16x8ShiftRightByScalar: { | 1819 case kArmI16x8ShrS: { |
1785 __ vshr(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0), | 1820 __ vshr(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1786 i.InputInt4(1)); | 1821 i.InputInt4(1)); |
1787 break; | 1822 break; |
1788 } | 1823 } |
1789 case kArmInt16x8Add: { | 1824 case kArmI16x8Eq: { |
1790 __ vadd(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1791 i.InputSimd128Register(1)); | |
1792 break; | |
1793 } | |
1794 case kArmInt16x8AddSaturate: { | |
1795 __ vqadd(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1796 i.InputSimd128Register(1)); | |
1797 break; | |
1798 } | |
1799 case kArmInt16x8Sub: { | |
1800 __ vsub(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1801 i.InputSimd128Register(1)); | |
1802 break; | |
1803 } | |
1804 case kArmInt16x8SubSaturate: { | |
1805 __ vqsub(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1806 i.InputSimd128Register(1)); | |
1807 break; | |
1808 } | |
1809 case kArmInt16x8Mul: { | |
1810 __ vmul(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1811 i.InputSimd128Register(1)); | |
1812 break; | |
1813 } | |
1814 case kArmInt16x8Min: { | |
1815 __ vmin(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1816 i.InputSimd128Register(1)); | |
1817 break; | |
1818 } | |
1819 case kArmInt16x8Max: { | |
1820 __ vmax(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1821 i.InputSimd128Register(1)); | |
1822 break; | |
1823 } | |
1824 case kArmInt16x8Equal: { | |
1825 __ vceq(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0), | 1825 __ vceq(Neon16, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1826 i.InputSimd128Register(1)); | 1826 i.InputSimd128Register(1)); |
1827 break; | 1827 break; |
1828 } | 1828 } |
1829 case kArmInt16x8NotEqual: { | 1829 case kArmI16x8Ne: { |
1830 Simd128Register dst = i.OutputSimd128Register(); | 1830 Simd128Register dst = i.OutputSimd128Register(); |
1831 __ vceq(Neon16, dst, i.InputSimd128Register(0), | 1831 __ vceq(Neon16, dst, i.InputSimd128Register(0), |
1832 i.InputSimd128Register(1)); | 1832 i.InputSimd128Register(1)); |
1833 __ vmvn(dst, dst); | 1833 __ vmvn(dst, dst); |
1834 break; | 1834 break; |
1835 } | 1835 } |
1836 case kArmInt16x8LessThan: { | 1836 case kArmI16x8LtS: { |
1837 __ vcgt(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(1), | 1837 __ vcgt(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(1), |
1838 i.InputSimd128Register(0)); | 1838 i.InputSimd128Register(0)); |
1839 break; | 1839 break; |
1840 } | 1840 } |
1841 case kArmInt16x8LessThanOrEqual: { | 1841 case kArmI16x8LeS: { |
1842 __ vcge(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(1), | 1842 __ vcge(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(1), |
1843 i.InputSimd128Register(0)); | 1843 i.InputSimd128Register(0)); |
1844 break; | 1844 break; |
1845 } | 1845 } |
1846 case kArmUint16x8ShiftRightByScalar: { | 1846 case kArmI16x8AddSaturateU: { |
1847 __ vqadd(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1848 i.InputSimd128Register(1)); | |
1849 break; | |
1850 } | |
1851 case kArmI16x8SubSaturateU: { | |
1852 __ vqsub(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1853 i.InputSimd128Register(1)); | |
1854 break; | |
1855 } | |
1856 case kArmI16x8MinU: { | |
1857 __ vmin(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1858 i.InputSimd128Register(1)); | |
1859 break; | |
1860 } | |
1861 case kArmI16x8MaxU: { | |
1862 __ vmax(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1863 i.InputSimd128Register(1)); | |
1864 break; | |
1865 } | |
1866 case kArmI16x8ShrU: { | |
1847 __ vshr(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0), | 1867 __ vshr(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1848 i.InputInt4(1)); | 1868 i.InputInt4(1)); |
1849 break; | 1869 break; |
1850 } | 1870 } |
1851 case kArmUint16x8AddSaturate: { | 1871 case kArmI16x8LtU: { |
1852 __ vqadd(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1853 i.InputSimd128Register(1)); | |
1854 break; | |
1855 } | |
1856 case kArmUint16x8SubSaturate: { | |
1857 __ vqsub(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1858 i.InputSimd128Register(1)); | |
1859 break; | |
1860 } | |
1861 case kArmUint16x8Min: { | |
1862 __ vmin(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1863 i.InputSimd128Register(1)); | |
1864 break; | |
1865 } | |
1866 case kArmUint16x8Max: { | |
1867 __ vmax(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1868 i.InputSimd128Register(1)); | |
1869 break; | |
1870 } | |
1871 case kArmUint16x8LessThan: { | |
1872 __ vcgt(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(1), | 1872 __ vcgt(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(1), |
1873 i.InputSimd128Register(0)); | 1873 i.InputSimd128Register(0)); |
1874 break; | 1874 break; |
1875 } | 1875 } |
1876 case kArmUint16x8LessThanOrEqual: { | 1876 case kArmI16x8LeU: { |
1877 __ vcge(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(1), | 1877 __ vcge(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(1), |
1878 i.InputSimd128Register(0)); | 1878 i.InputSimd128Register(0)); |
1879 break; | 1879 break; |
1880 } | 1880 } |
1881 case kArmInt8x16Splat: { | 1881 case kArmI8x16Splat: { |
1882 __ vdup(Neon8, i.OutputSimd128Register(), i.InputRegister(0)); | 1882 __ vdup(Neon8, i.OutputSimd128Register(), i.InputRegister(0)); |
1883 break; | 1883 break; |
1884 } | 1884 } |
1885 case kArmInt8x16ExtractLane: { | 1885 case kArmI8x16ExtractLane: { |
1886 __ ExtractLane(i.OutputRegister(), i.InputSimd128Register(0), NeonS8, | 1886 __ ExtractLane(i.OutputRegister(), i.InputSimd128Register(0), NeonS8, |
1887 i.InputInt8(1)); | 1887 i.InputInt8(1)); |
1888 break; | 1888 break; |
1889 } | 1889 } |
1890 case kArmInt8x16ReplaceLane: { | 1890 case kArmI8x16ReplaceLane: { |
1891 __ ReplaceLane(i.OutputSimd128Register(), i.InputSimd128Register(0), | 1891 __ ReplaceLane(i.OutputSimd128Register(), i.InputSimd128Register(0), |
1892 i.InputRegister(2), NeonS8, i.InputInt8(1)); | 1892 i.InputRegister(2), NeonS8, i.InputInt8(1)); |
1893 break; | 1893 break; |
1894 } | 1894 } |
1895 case kArmInt8x16Neg: { | 1895 case kArmI8x16Neg: { |
1896 __ vneg(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0)); | 1896 __ vneg(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0)); |
1897 break; | 1897 break; |
1898 } | 1898 } |
1899 case kArmInt8x16ShiftLeftByScalar: { | 1899 case kArmI8x16Add: { |
1900 __ vadd(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1901 i.InputSimd128Register(1)); | |
1902 break; | |
1903 } | |
1904 case kArmI8x16AddSaturate: { | |
1905 __ vqadd(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1906 i.InputSimd128Register(1)); | |
1907 break; | |
1908 } | |
1909 case kArmI8x16Sub: { | |
1910 __ vsub(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1911 i.InputSimd128Register(1)); | |
1912 break; | |
1913 } | |
1914 case kArmI8x16SubSaturate: { | |
1915 __ vqsub(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1916 i.InputSimd128Register(1)); | |
1917 break; | |
1918 } | |
1919 case kArmI8x16Mul: { | |
1920 __ vmul(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1921 i.InputSimd128Register(1)); | |
1922 break; | |
1923 } | |
1924 case kArmI8x16MinS: { | |
1925 __ vmin(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1926 i.InputSimd128Register(1)); | |
1927 break; | |
1928 } | |
1929 case kArmI8x16MaxS: { | |
1930 __ vmax(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1931 i.InputSimd128Register(1)); | |
1932 break; | |
1933 } | |
1934 case kArmI8x16Shl: { | |
1900 __ vshl(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0), | 1935 __ vshl(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1901 i.InputInt3(1)); | 1936 i.InputInt3(1)); |
1902 break; | 1937 break; |
1903 } | 1938 } |
1904 case kArmInt8x16ShiftRightByScalar: { | 1939 case kArmI8x16ShrS: { |
1905 __ vshr(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0), | 1940 __ vshr(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1906 i.InputInt3(1)); | 1941 i.InputInt3(1)); |
1907 break; | 1942 break; |
1908 } | 1943 } |
1909 case kArmInt8x16Add: { | 1944 case kArmI8x16Eq: { |
1910 __ vadd(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1911 i.InputSimd128Register(1)); | |
1912 break; | |
1913 } | |
1914 case kArmInt8x16AddSaturate: { | |
1915 __ vqadd(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1916 i.InputSimd128Register(1)); | |
1917 break; | |
1918 } | |
1919 case kArmInt8x16Sub: { | |
1920 __ vsub(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1921 i.InputSimd128Register(1)); | |
1922 break; | |
1923 } | |
1924 case kArmInt8x16SubSaturate: { | |
1925 __ vqsub(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1926 i.InputSimd128Register(1)); | |
1927 break; | |
1928 } | |
1929 case kArmInt8x16Mul: { | |
1930 __ vmul(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1931 i.InputSimd128Register(1)); | |
1932 break; | |
1933 } | |
1934 case kArmInt8x16Min: { | |
1935 __ vmin(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1936 i.InputSimd128Register(1)); | |
1937 break; | |
1938 } | |
1939 case kArmInt8x16Max: { | |
1940 __ vmax(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1941 i.InputSimd128Register(1)); | |
1942 break; | |
1943 } | |
1944 case kArmInt8x16Equal: { | |
1945 __ vceq(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0), | 1945 __ vceq(Neon8, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1946 i.InputSimd128Register(1)); | 1946 i.InputSimd128Register(1)); |
1947 break; | 1947 break; |
1948 } | 1948 } |
1949 case kArmInt8x16NotEqual: { | 1949 case kArmI8x16Ne: { |
1950 Simd128Register dst = i.OutputSimd128Register(); | 1950 Simd128Register dst = i.OutputSimd128Register(); |
1951 __ vceq(Neon8, dst, i.InputSimd128Register(0), i.InputSimd128Register(1)); | 1951 __ vceq(Neon8, dst, i.InputSimd128Register(0), i.InputSimd128Register(1)); |
1952 __ vmvn(dst, dst); | 1952 __ vmvn(dst, dst); |
1953 break; | 1953 break; |
1954 } | 1954 } |
1955 case kArmInt8x16LessThan: { | 1955 case kArmI8x16LtS: { |
1956 __ vcgt(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(1), | 1956 __ vcgt(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(1), |
1957 i.InputSimd128Register(0)); | 1957 i.InputSimd128Register(0)); |
1958 break; | 1958 break; |
1959 } | 1959 } |
1960 case kArmInt8x16LessThanOrEqual: { | 1960 case kArmI8x16LeS: { |
1961 __ vcge(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(1), | 1961 __ vcge(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(1), |
1962 i.InputSimd128Register(0)); | 1962 i.InputSimd128Register(0)); |
1963 break; | 1963 break; |
1964 } | 1964 } |
1965 case kArmUint8x16ShiftRightByScalar: { | 1965 case kArmI8x16AddSaturateU: { |
1966 __ vqadd(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1967 i.InputSimd128Register(1)); | |
1968 break; | |
1969 } | |
1970 case kArmI8x16SubSaturateU: { | |
1971 __ vqsub(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1972 i.InputSimd128Register(1)); | |
1973 break; | |
1974 } | |
1975 case kArmI8x16MinU: { | |
1976 __ vmin(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1977 i.InputSimd128Register(1)); | |
1978 break; | |
1979 } | |
1980 case kArmI8x16MaxU: { | |
1981 __ vmax(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1982 i.InputSimd128Register(1)); | |
1983 break; | |
1984 } | |
1985 case kArmI8x16ShrU: { | |
1966 __ vshr(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0), | 1986 __ vshr(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0), |
1967 i.InputInt3(1)); | 1987 i.InputInt3(1)); |
1968 break; | 1988 break; |
1969 } | 1989 } |
1970 case kArmUint8x16AddSaturate: { | 1990 case kArmI8x16LtU: { |
1971 __ vqadd(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1972 i.InputSimd128Register(1)); | |
1973 break; | |
1974 } | |
1975 case kArmUint8x16SubSaturate: { | |
1976 __ vqsub(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1977 i.InputSimd128Register(1)); | |
1978 break; | |
1979 } | |
1980 case kArmUint8x16Min: { | |
1981 __ vmin(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1982 i.InputSimd128Register(1)); | |
1983 break; | |
1984 } | |
1985 case kArmUint8x16Max: { | |
1986 __ vmax(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0), | |
1987 i.InputSimd128Register(1)); | |
1988 break; | |
1989 } | |
1990 case kArmUint8x16LessThan: { | |
1991 __ vcgt(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(1), | 1991 __ vcgt(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(1), |
1992 i.InputSimd128Register(0)); | 1992 i.InputSimd128Register(0)); |
1993 break; | 1993 break; |
1994 } | 1994 } |
1995 case kArmUint8x16LessThanOrEqual: { | 1995 case kArmI8x16LeU: { |
1996 __ vcge(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(1), | 1996 __ vcge(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(1), |
1997 i.InputSimd128Register(0)); | 1997 i.InputSimd128Register(0)); |
1998 break; | 1998 break; |
1999 } | 1999 } |
2000 case kArmSimd128Zero: { | 2000 case kArmS128Zero: { |
2001 __ veor(i.OutputSimd128Register(), i.OutputSimd128Register(), | 2001 __ veor(i.OutputSimd128Register(), i.OutputSimd128Register(), |
2002 i.OutputSimd128Register()); | 2002 i.OutputSimd128Register()); |
2003 break; | 2003 break; |
2004 } | 2004 } |
2005 case kArmSimd128And: { | 2005 case kArmS128And: { |
2006 __ vand(i.OutputSimd128Register(), i.InputSimd128Register(0), | 2006 __ vand(i.OutputSimd128Register(), i.InputSimd128Register(0), |
2007 i.InputSimd128Register(1)); | 2007 i.InputSimd128Register(1)); |
2008 break; | 2008 break; |
2009 } | 2009 } |
2010 case kArmSimd128Or: { | 2010 case kArmS128Or: { |
2011 __ vorr(i.OutputSimd128Register(), i.InputSimd128Register(0), | 2011 __ vorr(i.OutputSimd128Register(), i.InputSimd128Register(0), |
2012 i.InputSimd128Register(1)); | 2012 i.InputSimd128Register(1)); |
2013 break; | 2013 break; |
2014 } | 2014 } |
2015 case kArmSimd128Xor: { | 2015 case kArmS128Xor: { |
2016 __ veor(i.OutputSimd128Register(), i.InputSimd128Register(0), | 2016 __ veor(i.OutputSimd128Register(), i.InputSimd128Register(0), |
2017 i.InputSimd128Register(1)); | 2017 i.InputSimd128Register(1)); |
2018 break; | 2018 break; |
2019 } | 2019 } |
2020 case kArmSimd128Not: { | 2020 case kArmS128Not: { |
2021 __ vmvn(i.OutputSimd128Register(), i.InputSimd128Register(0)); | 2021 __ vmvn(i.OutputSimd128Register(), i.InputSimd128Register(0)); |
2022 break; | 2022 break; |
2023 } | 2023 } |
2024 case kArmSimd128Select: { | 2024 case kArmSimd128Select: { |
2025 // vbsl clobbers the mask input so make sure it was DefineSameAsFirst. | 2025 // vbsl clobbers the mask input so make sure it was DefineSameAsFirst. |
2026 DCHECK(i.OutputSimd128Register().is(i.InputSimd128Register(0))); | 2026 DCHECK(i.OutputSimd128Register().is(i.InputSimd128Register(0))); |
2027 __ vbsl(i.OutputSimd128Register(), i.InputSimd128Register(1), | 2027 __ vbsl(i.OutputSimd128Register(), i.InputSimd128Register(1), |
2028 i.InputSimd128Register(2)); | 2028 i.InputSimd128Register(2)); |
2029 break; | 2029 break; |
2030 } | 2030 } |
2031 case kArmSimd1x4AnyTrue: { | 2031 case kArmS1x4AnyTrue: { |
2032 const QwNeonRegister& src = i.InputSimd128Register(0); | 2032 const QwNeonRegister& src = i.InputSimd128Register(0); |
2033 __ vpmax(NeonU32, kScratchDoubleReg, src.low(), src.high()); | 2033 __ vpmax(NeonU32, kScratchDoubleReg, src.low(), src.high()); |
2034 __ vpmax(NeonU32, kScratchDoubleReg, kScratchDoubleReg, | 2034 __ vpmax(NeonU32, kScratchDoubleReg, kScratchDoubleReg, |
2035 kScratchDoubleReg); | 2035 kScratchDoubleReg); |
2036 __ ExtractLane(i.OutputRegister(), kScratchDoubleReg, NeonS32, 0); | 2036 __ ExtractLane(i.OutputRegister(), kScratchDoubleReg, NeonS32, 0); |
2037 break; | 2037 break; |
2038 } | 2038 } |
2039 case kArmSimd1x4AllTrue: { | 2039 case kArmS1x4AllTrue: { |
2040 const QwNeonRegister& src = i.InputSimd128Register(0); | 2040 const QwNeonRegister& src = i.InputSimd128Register(0); |
2041 __ vpmin(NeonU32, kScratchDoubleReg, src.low(), src.high()); | 2041 __ vpmin(NeonU32, kScratchDoubleReg, src.low(), src.high()); |
2042 __ vpmin(NeonU32, kScratchDoubleReg, kScratchDoubleReg, | 2042 __ vpmin(NeonU32, kScratchDoubleReg, kScratchDoubleReg, |
2043 kScratchDoubleReg); | 2043 kScratchDoubleReg); |
2044 __ ExtractLane(i.OutputRegister(), kScratchDoubleReg, NeonS32, 0); | 2044 __ ExtractLane(i.OutputRegister(), kScratchDoubleReg, NeonS32, 0); |
2045 break; | 2045 break; |
2046 } | 2046 } |
2047 case kArmSimd1x8AnyTrue: { | 2047 case kArmS1x8AnyTrue: { |
2048 const QwNeonRegister& src = i.InputSimd128Register(0); | 2048 const QwNeonRegister& src = i.InputSimd128Register(0); |
2049 __ vpmax(NeonU16, kScratchDoubleReg, src.low(), src.high()); | 2049 __ vpmax(NeonU16, kScratchDoubleReg, src.low(), src.high()); |
2050 __ vpmax(NeonU16, kScratchDoubleReg, kScratchDoubleReg, | 2050 __ vpmax(NeonU16, kScratchDoubleReg, kScratchDoubleReg, |
2051 kScratchDoubleReg); | 2051 kScratchDoubleReg); |
2052 __ vpmax(NeonU16, kScratchDoubleReg, kScratchDoubleReg, | 2052 __ vpmax(NeonU16, kScratchDoubleReg, kScratchDoubleReg, |
2053 kScratchDoubleReg); | 2053 kScratchDoubleReg); |
2054 __ ExtractLane(i.OutputRegister(), kScratchDoubleReg, NeonS16, 0); | 2054 __ ExtractLane(i.OutputRegister(), kScratchDoubleReg, NeonS16, 0); |
2055 break; | 2055 break; |
2056 } | 2056 } |
2057 case kArmSimd1x8AllTrue: { | 2057 case kArmS1x8AllTrue: { |
2058 const QwNeonRegister& src = i.InputSimd128Register(0); | 2058 const QwNeonRegister& src = i.InputSimd128Register(0); |
2059 __ vpmin(NeonU16, kScratchDoubleReg, src.low(), src.high()); | 2059 __ vpmin(NeonU16, kScratchDoubleReg, src.low(), src.high()); |
2060 __ vpmin(NeonU16, kScratchDoubleReg, kScratchDoubleReg, | 2060 __ vpmin(NeonU16, kScratchDoubleReg, kScratchDoubleReg, |
2061 kScratchDoubleReg); | 2061 kScratchDoubleReg); |
2062 __ vpmin(NeonU16, kScratchDoubleReg, kScratchDoubleReg, | 2062 __ vpmin(NeonU16, kScratchDoubleReg, kScratchDoubleReg, |
2063 kScratchDoubleReg); | 2063 kScratchDoubleReg); |
2064 __ ExtractLane(i.OutputRegister(), kScratchDoubleReg, NeonS16, 0); | 2064 __ ExtractLane(i.OutputRegister(), kScratchDoubleReg, NeonS16, 0); |
2065 break; | 2065 break; |
2066 } | 2066 } |
2067 case kArmSimd1x16AnyTrue: { | 2067 case kArmS1x16AnyTrue: { |
2068 const QwNeonRegister& src = i.InputSimd128Register(0); | 2068 const QwNeonRegister& src = i.InputSimd128Register(0); |
2069 __ vpmax(NeonU8, kScratchDoubleReg, src.low(), src.high()); | 2069 __ vpmax(NeonU8, kScratchDoubleReg, src.low(), src.high()); |
2070 __ vpmax(NeonU8, kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg); | 2070 __ vpmax(NeonU8, kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg); |
2071 // vtst to detect any bits in the bottom 32 bits of kScratchDoubleReg. | 2071 // vtst to detect any bits in the bottom 32 bits of kScratchDoubleReg. |
2072 // This saves an instruction vs. the naive sequence of vpmax. | 2072 // This saves an instruction vs. the naive sequence of vpmax. |
2073 // kDoubleRegZero is not changed, since it is 0. | 2073 // kDoubleRegZero is not changed, since it is 0. |
2074 __ vtst(Neon32, kScratchQuadReg, kScratchQuadReg, kScratchQuadReg); | 2074 __ vtst(Neon32, kScratchQuadReg, kScratchQuadReg, kScratchQuadReg); |
2075 __ ExtractLane(i.OutputRegister(), kScratchDoubleReg, NeonS32, 0); | 2075 __ ExtractLane(i.OutputRegister(), kScratchDoubleReg, NeonS32, 0); |
2076 break; | 2076 break; |
2077 } | 2077 } |
2078 case kArmSimd1x16AllTrue: { | 2078 case kArmS1x16AllTrue: { |
2079 const QwNeonRegister& src = i.InputSimd128Register(0); | 2079 const QwNeonRegister& src = i.InputSimd128Register(0); |
2080 __ vpmin(NeonU8, kScratchDoubleReg, src.low(), src.high()); | 2080 __ vpmin(NeonU8, kScratchDoubleReg, src.low(), src.high()); |
2081 __ vpmin(NeonU8, kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg); | 2081 __ vpmin(NeonU8, kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg); |
2082 __ vpmin(NeonU8, kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg); | 2082 __ vpmin(NeonU8, kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg); |
2083 __ vpmin(NeonU8, kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg); | 2083 __ vpmin(NeonU8, kScratchDoubleReg, kScratchDoubleReg, kScratchDoubleReg); |
2084 __ ExtractLane(i.OutputRegister(), kScratchDoubleReg, NeonS8, 0); | 2084 __ ExtractLane(i.OutputRegister(), kScratchDoubleReg, NeonS8, 0); |
2085 break; | 2085 break; |
2086 } | 2086 } |
2087 case kCheckedLoadInt8: | 2087 case kCheckedLoadInt8: |
2088 ASSEMBLE_CHECKED_LOAD_INTEGER(ldrsb); | 2088 ASSEMBLE_CHECKED_LOAD_INTEGER(ldrsb); |
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2831 padding_size -= v8::internal::Assembler::kInstrSize; | 2831 padding_size -= v8::internal::Assembler::kInstrSize; |
2832 } | 2832 } |
2833 } | 2833 } |
2834 } | 2834 } |
2835 | 2835 |
2836 #undef __ | 2836 #undef __ |
2837 | 2837 |
2838 } // namespace compiler | 2838 } // namespace compiler |
2839 } // namespace internal | 2839 } // namespace internal |
2840 } // namespace v8 | 2840 } // namespace v8 |
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