[ARM] Implement widening and narrowing integer moves, vmovl, vqmovn.

src/arm/disasm-arm.cc

Index: src/arm/disasm-arm.cc
diff --git a/src/arm/disasm-arm.cc b/src/arm/disasm-arm.cc
index efd407d9d4df7af6ab89d48c5fb4b855950b7c5f..8f52dc390bac6ac3b96c797976e5a63ae912ce78 100644
--- a/src/arm/disasm-arm.cc
+++ b/src/arm/disasm-arm.cc
@@ -1576,19 +1576,19 @@ void Decoder::DecodeTypeVFP(Instruction* instr) {
           Format(instr, "vmov'cond.32 'rt, 'Dd[1]");
         }
       } else {
-        const char* sign = instr->Bit(23) != 0 ? "u" : "s";
+        char sign = instr->Bit(23) != 0 ? 'u' : 's';
         int rt = instr->RtValue();
         int vn = instr->VFPNRegValue(kDoublePrecision);
         if ((opc1_opc2 & 0x8) != 0) {
           // NeonS8 / NeonU8
           int i = opc1_opc2 & 0x7;
           out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
-                                      "vmov.%s8 r%d, d%d[%d]", sign, rt, vn, i);
+                                      "vmov.%c8 r%d, d%d[%d]", sign, rt, vn, i);
         } else if ((opc1_opc2 & 0x1) != 0) {
           // NeonS16 / NeonU16
           int i = (opc1_opc2 >> 1) & 0x3;
           out_buffer_pos_ +=
-              SNPrintF(out_buffer_ + out_buffer_pos_, "vmov.%s16 r%d, d%d[%d]",
+              SNPrintF(out_buffer_ + out_buffer_pos_, "vmov.%c16 r%d, d%d[%d]",
                        sign, rt, vn, i);
         } else {
           Unknown(instr);
@@ -2166,8 +2166,7 @@ void Decoder::DecodeSpecialCondition(Instruction* instr) {
         int imm3 = instr->Bits(21, 19);
         out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
                                     "vmovl.u%d q%d, d%d", imm3 * 8, Vd, Vm);
-      } else if (instr->Opc1Value() == 7 && instr->Bits(21, 20) == 0x3 &&
-                 instr->Bit(4) == 0) {
+      } else if (instr->Opc1Value() == 7 && instr->Bit(4) == 0) {
         if (instr->Bits(17, 16) == 0x2 && instr->Bits(11, 7) == 0) {
           if (instr->Bit(6) == 0) {
             int Vd = instr->VFPDRegValue(kDoublePrecision);
@@ -2256,16 +2255,16 @@ void Decoder::DecodeSpecialCondition(Instruction* instr) {
           int Vd = instr->VFPDRegValue(kSimd128Precision);
           int Vm = instr->VFPMRegValue(kSimd128Precision);
           int size = kBitsPerByte * (1 << instr->Bits(19, 18));
-          const char* type = instr->Bit(10) != 0 ? "f" : "s";
+          char type = instr->Bit(10) != 0 ? 'f' : 's';
           if (instr->Bits(9, 6) == 0xd) {
             // vabs<type>.<size> Qd, Qm.
             out_buffer_pos_ +=
-                SNPrintF(out_buffer_ + out_buffer_pos_, "vabs.%s%d q%d, q%d",
+                SNPrintF(out_buffer_ + out_buffer_pos_, "vabs.%c%d q%d, q%d",
                          type, size, Vd, Vm);
           } else if (instr->Bits(9, 6) == 0xf) {
             // vneg<type>.<size> Qd, Qm.
             out_buffer_pos_ +=
-                SNPrintF(out_buffer_ + out_buffer_pos_, "vneg.%s%d q%d, q%d",
+                SNPrintF(out_buffer_ + out_buffer_pos_, "vneg.%c%d q%d, q%d",
                          type, size, Vd, Vm);
           } else {
             Unknown(instr);
@@ -2278,6 +2277,16 @@ void Decoder::DecodeSpecialCondition(Instruction* instr) {
           const char* op = instr->Bit(7) == 0 ? "vrecpe" : "vrsqrte";
           out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
                                       "%s.f32 q%d, q%d", op, Vd, Vm);
+        } else if (instr->Bits(17, 16) == 0x2 && instr->Bits(11, 8) == 0x2 &&
+                   instr->Bits(7, 6) != 0) {
+          // vqmovn.<type><size> Dd, Qm.
+          int Vd = instr->VFPDRegValue(kDoublePrecision);
+          int Vm = instr->VFPMRegValue(kSimd128Precision);
+          char type = instr->Bit(6) != 0 ? 'u' : 's';
+          int size = 2 * kBitsPerByte * (1 << instr->Bits(19, 18));
+          out_buffer_pos_ +=
+              SNPrintF(out_buffer_ + out_buffer_pos_, "vqmovn.%c%i d%d, q%d",
+                       type, size, Vd, Vm);
         } else {
           Unknown(instr);
         }