[ARM] Implement widening and narrowing integer moves, vmovl, vqmovn.

test/cctest/test-assembler-arm.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 1263 matching lines @@
     uint32_t dst4;
     uint32_t dst5;
     uint32_t dst6;
     uint32_t dst7;
     uint32_t srcA0;
     uint32_t srcA1;
     uint32_t dstA0;
     uint32_t dstA1;
     uint32_t dstA2;
     uint32_t dstA3;
-    uint32_t dstA4;
-    uint32_t dstA5;
-    uint32_t dstA6;
-    uint32_t dstA7;
     uint32_t lane_test[4];
     uint64_t vmov_to_scalar1, vmov_to_scalar2;
     uint32_t vmov_from_scalar_s8, vmov_from_scalar_u8;
     uint32_t vmov_from_scalar_s16, vmov_from_scalar_u16;
     uint32_t vmov_from_scalar_32;
     uint32_t vmov[4], vmvn[4];
+    uint32_t vmovl_s8[4], vmovl_u16[4], vmovl_s32[4];
+    uint32_t vqmovn_s8[2], vqmovn_u16[2], vqmovn_s32[2];
     int32_t vcvt_s32_f32[4];
     uint32_t vcvt_u32_f32[4];
     float vcvt_f32_s32[4], vcvt_f32_u32[4];
     uint32_t vdup8[4], vdup16[4], vdup32[4];
     float vabsf[4], vnegf[4];
     uint32_t vabs_s8[4], vabs_s16[4], vabs_s32[4];
     uint32_t vneg_s8[4], vneg_s16[4], vneg_s32[4];
     uint32_t veor[4], vand[4], vorr[4];
     float vdupf[4], vaddf[4], vsubf[4], vmulf[4];
     uint32_t vmin_s8[4], vmin_u16[4], vmin_s32[4];
@@ skipping 43 matching lines @@
     // Expand 8 bytes into 8 words(16 bits).
     __ add(r4, r0, Operand(static_cast<int32_t>(offsetof(T, srcA0))));
     __ vld1(Neon8, NeonListOperand(d0), NeonMemOperand(r4));
     __ vmovl(NeonU8, q0, d0);
     __ add(r4, r0, Operand(static_cast<int32_t>(offsetof(T, dstA0))));
     __ vst1(Neon8, NeonListOperand(d0, 2), NeonMemOperand(r4));
 
     // The same expansion, but with different source and destination registers.
     __ add(r4, r0, Operand(static_cast<int32_t>(offsetof(T, srcA0))));
     __ vld1(Neon8, NeonListOperand(d1), NeonMemOperand(r4));
-    __ vmovl(NeonU8, q1, d1);
-    __ add(r4, r0, Operand(static_cast<int32_t>(offsetof(T, dstA4))));
-    __ vst1(Neon8, NeonListOperand(d2, 2), NeonMemOperand(r4));
+    __ vmovl(NeonS8, q1, d1);
+    __ add(r4, r0, Operand(static_cast<int32_t>(offsetof(T, vmovl_s8))));
+    __ vst1(Neon8, NeonListOperand(q1), NeonMemOperand(r4));
+    __ vmovl(NeonU16, q2, d3);
+    __ add(r4, r0, Operand(static_cast<int32_t>(offsetof(T, vmovl_u16))));
+    __ vst1(Neon8, NeonListOperand(q2), NeonMemOperand(r4));
+    __ vmovl(NeonS32, q3, d4);
+    __ add(r4, r0, Operand(static_cast<int32_t>(offsetof(T, vmovl_s32))));
+    __ vst1(Neon8, NeonListOperand(q3), NeonMemOperand(r4));
+    // Narrow what we widened.
+    __ vqmovn(NeonU16, d0, q2);
+    __ vstr(d0, r0, offsetof(T, vqmovn_u16));
+    __ vmov(d1, d0);
+    __ vqmovn(NeonS8, d2, q0);
+    __ vstr(d2, r0, offsetof(T, vqmovn_s8));
+    __ vqmovn(NeonS32, d4, q3);
+    __ vstr(d4, r0, offsetof(T, vqmovn_s32));
 
     // ARM core register to scalar.
     __ mov(r4, Operand(0xfffffff8));
     __ vmov(d0, 0);
     __ vmov(NeonS8, d0, 1, r4);
     __ vmov(NeonS16, d0, 1, r4);
     __ vmov(NeonS32, d0, 1, r4);
     __ vstr(d0, r0, offsetof(T, vmov_to_scalar1));
     __ vmov(d0, 0);
     __ vmov(NeonS8, d0, 3, r4);
@@ skipping 610 matching lines @@
     t.dst4 = 0;
     t.dst5 = 0;
     t.dst6 = 0;
     t.dst7 = 0;
     t.srcA0 = 0x41424344;
     t.srcA1 = 0x81828384;
     t.dstA0 = 0;
     t.dstA1 = 0;
     t.dstA2 = 0;
     t.dstA3 = 0;
-    t.dstA4 = 0;
-    t.dstA5 = 0;
-    t.dstA6 = 0;
-    t.dstA7 = 0;
     t.lane_test[0] = 0x03020100;
     t.lane_test[1] = 0x07060504;
     t.lane_test[2] = 0x0b0a0908;
     t.lane_test[3] = 0x0f0e0d0c;
     Object* dummy = CALL_GENERATED_CODE(isolate, f, &t, 0, 0, 0, 0);
     USE(dummy);
 
     CHECK_EQ(0x01020304u, t.dst0);
     CHECK_EQ(0x11121314u, t.dst1);
     CHECK_EQ(0x21222324u, t.dst2);
     CHECK_EQ(0x31323334u, t.dst3);
     CHECK_EQ(0x41424344u, t.dst4);
     CHECK_EQ(0x51525354u, t.dst5);
     CHECK_EQ(0x61626364u, t.dst6);
     CHECK_EQ(0x71727374u, t.dst7);
     CHECK_EQ(0x00430044u, t.dstA0);
     CHECK_EQ(0x00410042u, t.dstA1);
     CHECK_EQ(0x00830084u, t.dstA2);
     CHECK_EQ(0x00810082u, t.dstA3);
-    CHECK_EQ(0x00430044u, t.dstA4);
-    CHECK_EQ(0x00410042u, t.dstA5);
-    CHECK_EQ(0x00830084u, t.dstA6);
-    CHECK_EQ(0x00810082u, t.dstA7);
+
+    CHECK_EQ_32X4(vmovl_s8, 0x00430044u, 0x00410042u, 0xff83ff84u, 0xff81ff82u);
+    CHECK_EQ_32X4(vmovl_u16, 0xff84u, 0xff83u, 0xff82u, 0xff81u);
+    CHECK_EQ_32X4(vmovl_s32, 0xff84u, 0x0u, 0xff83u, 0x0u);
+    CHECK_EQ_32X2(vqmovn_u16, 0xff83ff84u, 0xff81ff82u);
+    CHECK_EQ_32X2(vqmovn_s8, 0x81828384u, 0x81828384u);
+    CHECK_EQ_32X2(vqmovn_s32, 0xff84u, 0xff83u);
 
     CHECK_EQ(0xfffffff8fff8f800u, t.vmov_to_scalar1);
     CHECK_EQ(0xfff80000f8000000u, t.vmov_to_scalar2);
     CHECK_EQ(0xFFFFFFFFu, t.vmov_from_scalar_s8);
     CHECK_EQ(0xFFu, t.vmov_from_scalar_u8);
     CHECK_EQ(0xFFFFFFFFu, t.vmov_from_scalar_s16);
     CHECK_EQ(0xFFFFu, t.vmov_from_scalar_u16);
     CHECK_EQ(0xFFFFFFFFu, t.vmov_from_scalar_32);
 
     CHECK_EQ_32X4(vmov, 0x03020100u, 0x07060504u, 0x0b0a0908u, 0x0f0e0d0cu);
@@ skipping 1806 matching lines @@
   HandleScope scope(isolate);
 
   Assembler assm(isolate, NULL, 0);
   __ mov(r0, Operand(isolate->factory()->infinity_value()));
   __ BlockConstPoolFor(1019);
   for (int i = 0; i < 1019; ++i) __ nop();
   __ vldr(d0, MemOperand(r0, 0));
 }
 
 #undef __