[ARM] Implement widening and narrowing integer moves, vmovl, vqmovn.

src/arm/disasm-arm.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 // A Disassembler object is used to disassemble a block of code instruction by
 // instruction. The default implementation of the NameConverter object can be
 // overriden to modify register names or to do symbol lookup on addresses.
 //
 // The example below will disassemble a block of code and print it to stdout.
 //
@@ skipping 1558 matching lines @@
     } else if ((instr->VLValue() == 0x1) && (instr->VCValue() == 0x1)) {
       int opc1_opc2 = (instr->Bits(22, 21) << 2) | instr->Bits(6, 5);
       if ((opc1_opc2 & 0xb) == 0) {
         // NeonS32 / NeonU32
         if (instr->Bit(21) == 0x0) {
           Format(instr, "vmov'cond.32 'rt, 'Dd[0]");
         } else {
           Format(instr, "vmov'cond.32 'rt, 'Dd[1]");
         }
       } else {
-        const char* sign = instr->Bit(23) != 0 ? "u" : "s";
+        char sign = instr->Bit(23) != 0 ? 'u' : 's';
         int rt = instr->RtValue();
         int vn = instr->VFPNRegValue(kDoublePrecision);
         if ((opc1_opc2 & 0x8) != 0) {
           // NeonS8 / NeonU8
           int i = opc1_opc2 & 0x7;
           out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
-                                      "vmov.%s8 r%d, d%d[%d]", sign, rt, vn, i);
+                                      "vmov.%c8 r%d, d%d[%d]", sign, rt, vn, i);
         } else if ((opc1_opc2 & 0x1) != 0) {
           // NeonS16 / NeonU16
           int i = (opc1_opc2 >> 1) & 0x3;
           out_buffer_pos_ +=
-              SNPrintF(out_buffer_ + out_buffer_pos_, "vmov.%s16 r%d, d%d[%d]",
+              SNPrintF(out_buffer_ + out_buffer_pos_, "vmov.%c16 r%d, d%d[%d]",
                        sign, rt, vn, i);
         } else {
           Unknown(instr);
         }
       }
     } else if ((instr->VCValue() == 0x0) &&
                (instr->VAValue() == 0x7) &&
                (instr->Bits(19, 16) == 0x1)) {
       if (instr->VLValue() == 0) {
         if (instr->Bits(15, 12) == 0xF) {
@@ skipping 557 matching lines @@
     case 7:
       if ((instr->Bits(18, 16) == 0) && (instr->Bits(11, 6) == 0x28) &&
           (instr->Bit(4) == 1)) {
         // vmovl unsigned
         if ((instr->VdValue() & 1) != 0) Unknown(instr);
         int Vd = (instr->Bit(22) << 3) | (instr->VdValue() >> 1);
         int Vm = (instr->Bit(5) << 4) | instr->VmValue();
         int imm3 = instr->Bits(21, 19);
         out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
                                     "vmovl.u%d q%d, d%d", imm3 * 8, Vd, Vm);
-      } else if (instr->Opc1Value() == 7 && instr->Bits(21, 20) == 0x3 &&
-                 instr->Bit(4) == 0) {
+      } else if (instr->Opc1Value() == 7 && instr->Bit(4) == 0) {
         if (instr->Bits(17, 16) == 0x2 && instr->Bits(11, 7) == 0) {
           if (instr->Bit(6) == 0) {
             int Vd = instr->VFPDRegValue(kDoublePrecision);
             int Vm = instr->VFPMRegValue(kDoublePrecision);
             out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
                                         "vswp d%d, d%d", Vd, Vm);
           } else {
             int Vd = instr->VFPDRegValue(kSimd128Precision);
             int Vm = instr->VFPMRegValue(kSimd128Precision);
             out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
@@ skipping 68 matching lines @@
           int Vm = instr->VFPMRegValue(kSimd128Precision);
           int size = kBitsPerByte * (1 << instr->Bits(19, 18));
           // vtrn.<size> Qd, Qm.
           out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
                                       "vtrn.%d q%d, q%d", size, Vd, Vm);
         } else if (instr->Bits(17, 16) == 0x1 && instr->Bit(11) == 0 &&
                    instr->Bit(6) == 1) {
           int Vd = instr->VFPDRegValue(kSimd128Precision);
           int Vm = instr->VFPMRegValue(kSimd128Precision);
           int size = kBitsPerByte * (1 << instr->Bits(19, 18));
-          const char* type = instr->Bit(10) != 0 ? "f" : "s";
+          char type = instr->Bit(10) != 0 ? 'f' : 's';
           if (instr->Bits(9, 6) == 0xd) {
             // vabs<type>.<size> Qd, Qm.
             out_buffer_pos_ +=
-                SNPrintF(out_buffer_ + out_buffer_pos_, "vabs.%s%d q%d, q%d",
+                SNPrintF(out_buffer_ + out_buffer_pos_, "vabs.%c%d q%d, q%d",
                          type, size, Vd, Vm);
           } else if (instr->Bits(9, 6) == 0xf) {
             // vneg<type>.<size> Qd, Qm.
             out_buffer_pos_ +=
-                SNPrintF(out_buffer_ + out_buffer_pos_, "vneg.%s%d q%d, q%d",
+                SNPrintF(out_buffer_ + out_buffer_pos_, "vneg.%c%d q%d, q%d",
                          type, size, Vd, Vm);
           } else {
             Unknown(instr);
           }
         } else if (instr->Bits(19, 18) == 0x2 && instr->Bits(11, 8) == 0x5 &&
                    instr->Bit(6) == 1) {
           // vrecpe/vrsqrte.f32 Qd, Qm.
           int Vd = instr->VFPDRegValue(kSimd128Precision);
           int Vm = instr->VFPMRegValue(kSimd128Precision);
           const char* op = instr->Bit(7) == 0 ? "vrecpe" : "vrsqrte";
           out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
                                       "%s.f32 q%d, q%d", op, Vd, Vm);
+        } else if (instr->Bits(17, 16) == 0x2 && instr->Bits(11, 8) == 0x2 &&
+                   instr->Bits(7, 6) != 0) {
+          // vqmovn.<type><size> Dd, Qm.
+          int Vd = instr->VFPDRegValue(kDoublePrecision);
+          int Vm = instr->VFPMRegValue(kSimd128Precision);
+          char type = instr->Bit(6) != 0 ? 'u' : 's';
+          int size = 2 * kBitsPerByte * (1 << instr->Bits(19, 18));
+          out_buffer_pos_ +=
+              SNPrintF(out_buffer_ + out_buffer_pos_, "vqmovn.%c%i d%d, q%d",
+                       type, size, Vd, Vm);
         } else {
           Unknown(instr);
         }
       } else if (instr->Bits(11, 7) == 0 && instr->Bit(4) == 1 &&
                  instr->Bit(6) == 1) {
         // vshr.u<size> Qd, Qm, shift
         int size = base::bits::RoundDownToPowerOfTwo32(instr->Bits(21, 16));
         int shift = 2 * size - instr->Bits(21, 16);
         int Vd = instr->VFPDRegValue(kSimd128Precision);
         int Vm = instr->VFPMRegValue(kSimd128Precision);
@@ skipping 338 matching lines @@
     pc += d.InstructionDecode(buffer, pc);
     v8::internal::PrintF(f, "%p    %08x      %s\n", static_cast<void*>(prev_pc),
                          *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
   }
 }
 
 
 }  // namespace disasm
 
 #endif  // V8_TARGET_ARCH_ARM