[ARM] Implement widening and narrowing integer moves, vmovl, vqmovn.

src/arm/assembler-arm.cc

 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions
 // are met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
 //
@@ skipping 3901 matching lines @@
   int vd, d;
   dst.split_code(&vd, &d);
   int vm, m;
   src.split_code(&vm, &m);
   int U = NeonU(dt);
   int imm3 = 1 << NeonSz(dt);
   emit(0xFU * B28 | B25 | U * B24 | B23 | d * B22 | imm3 * B19 | vd * B12 |
        0xA * B8 | m * B5 | B4 | vm);
 }
 
+void Assembler::vqmovn(NeonDataType dt, DwVfpRegister dst, QwNeonRegister src) {
+  // Instruction details available in ARM DDI 0406C.b, A8.8.1004.
+  // vqmovn.<type><size> Dd, Qm. ARM vector narrowing move with saturation.
+  DCHECK(IsEnabled(NEON));
+  int vd, d;
+  dst.split_code(&vd, &d);
+  int vm, m;
+  src.split_code(&vm, &m);
+  int size = NeonSz(dt);
+  int u = NeonU(dt);
+  int op = u != 0 ? 3 : 2;
+  emit(0x1E7U * B23 | d * B22 | 0x3 * B20 | size * B18 | 0x2 * B16 | vd * B12 |
+       0x2 * B8 | op * B6 | m * B5 | vm);
+}
+
 static int EncodeScalar(NeonDataType dt, int index) {
   int opc1_opc2 = 0;
   DCHECK_LE(0, index);
   switch (dt) {
     case NeonS8:
     case NeonU8:
       DCHECK_GT(8, index);
       opc1_opc2 = 0x8 | index;
       break;
     case NeonS16:
@@ skipping 1440 matching lines @@
 }
 
 void PatchingAssembler::FlushICache(Isolate* isolate) {
   Assembler::FlushICache(isolate, buffer_, buffer_size_ - kGap);
 }
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_TARGET_ARCH_ARM