Add pshufw instruction, fix inconsistencies with pextrw instruction.

src/x64/assembler-x64.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/x64/assembler-x64.h"
 
 #include <cstring>
 
 #if V8_TARGET_ARCH_X64
 
@@ skipping 816 matching lines @@
 
 
 void Assembler::bsfq(Register dst, const Operand& src) {
   EnsureSpace ensure_space(this);
   emit_rex_64(dst, src);
   emit(0x0F);
   emit(0xBC);
   emit_operand(dst, src);
 }
 
+void Assembler::pshufw(XMMRegister dst, XMMRegister src, uint8_t shuffle) {
+  EnsureSpace ensure_space(this);
+  emit_optional_rex_32(dst, src);
+  emit(0x0F);
+  emit(0x70);
+  emit(0xC0 | (dst.low_bits() << 3) | src.low_bits());
+  emit(shuffle);
+}
+
+void Assembler::pshufw(XMMRegister dst, const Operand& src, uint8_t shuffle) {
+  EnsureSpace ensure_space(this);
+  emit_optional_rex_32(dst, src);
+  emit(0x0F);
+  emit(0x70);
+  emit_operand(dst.code(), src);
+  emit(shuffle);
+}
 
 void Assembler::call(Label* L) {
   EnsureSpace ensure_space(this);
   // 1110 1000 #32-bit disp.
   emit(0xE8);
   if (L->is_bound()) {
     int offset = L->pos() - pc_offset() - sizeof(int32_t);
     DCHECK(offset <= 0);
     emitl(offset);
   } else if (L->is_linked()) {
@@ skipping 2017 matching lines @@
   EnsureSpace ensure_space(this);
   emit(0x66);
   emit_optional_rex_32(dst, src);
   emit(0x0F);
   emit(0xC4);
   emit_sse_operand(dst, src);
   emit(imm8);
 }
 
 void Assembler::pextrw(Register dst, XMMRegister src, int8_t imm8) {
+  DCHECK(IsEnabled(SSE4_1));
   DCHECK(is_uint8(imm8));

[bbudge, 2017/03/22 19:17:05]

If I'm reading the docs correctly, this could be even stronger: DCHECK_GT(8,
imm8);

[gdeepti, 2017/03/22 20:45:34]

A agree that this check could be stronger, but I'm not sure if the assembler is
the right place for the check as the instructions only specifies that the count
operand is an 8-bit immediate, and only the 3 least-significant bits are used
for location. We already check this in the validate function on decode, will add
a check in the code generator before it comes to the assembler.  

[bbudge, 2017/03/22 21:09:40]

OK

   EnsureSpace ensure_space(this);
   emit(0x66);
-  emit_optional_rex_32(src, dst);
+  emit_optional_rex_32(dst, src);
   emit(0x0F);
-  emit(0xC5);
-  emit_sse_operand(src, dst);
+  emit(0x3A);
+  emit(0x15);
+  emit_sse_operand(dst, src);
   emit(imm8);
 }
 
 void Assembler::pextrw(const Operand& dst, XMMRegister src, int8_t imm8) {
   DCHECK(IsEnabled(SSE4_1));
   DCHECK(is_uint8(imm8));
   EnsureSpace ensure_space(this);
   emit(0x66);
   emit_optional_rex_32(src, dst);
   emit(0x0F);
@@ skipping 1856 matching lines @@
 
 bool RelocInfo::IsInConstantPool() {
   return false;
 }
 
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_TARGET_ARCH_X64