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Side by Side Diff: tests_lit/llvm2ice_tests/64bit.pnacl.ll

Issue 277033003: Modify pnacl subzero to be able to read pnacl bitcode files. (Closed) Base URL: https://gerrit.chromium.org/gerrit/p/native_client/pnacl-subzero.git@master
Patch Set: Fix nits. Created 6 years, 7 months ago
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1 ; RUIN: %llvm2ice --verbose none %s | FileCheck %s 1 ; RUIN: %llvm2ice --verbose none %s | FileCheck %s
2 ; RUIN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s 2 ; RUIN: %llvm2ice --verbose none %s | FileCheck --check-prefix=ERRORS %s
3 ; RUN: %szdiff --llvm2ice=%llvm2ice %s | FileCheck --check-prefix=DUMP %s 3 ; RUN: %llvm2iceinsts %s | %szdiff %s | FileCheck --check-prefix=DUMP %s
4 ; RUN: %llvm2iceinsts --pnacl %s | %szdiff %s \
5 ; RUN: | FileCheck --check-prefix=DUMP %s
4 6
5 @__init_array_start = internal constant [0 x i8] zeroinitializer, align 4 7 @__init_array_start = internal constant [0 x i8] zeroinitializer, align 4
6 @__fini_array_start = internal constant [0 x i8] zeroinitializer, align 4 8 @__fini_array_start = internal constant [0 x i8] zeroinitializer, align 4
7 @__tls_template_start = internal constant [0 x i8] zeroinitializer, align 8 9 @__tls_template_start = internal constant [0 x i8] zeroinitializer, align 8
8 @__tls_template_alignment = internal constant [4 x i8] c"\01\00\00\00", align 4 10 @__tls_template_alignment = internal constant [4 x i8] c"\01\00\00\00", align 4
9 11
10 define internal i32 @ignore64BitArg(i64 %a, i32 %b, i64 %c) { 12 define internal i32 @ignore64BitArg(i64 %a, i32 %b, i64 %c) {
11 entry: 13 entry:
12 ret i32 %b 14 ret i32 %b
13 } 15 }
(...skipping 698 matching lines...) Expand 10 before | Expand all | Expand 10 after
712 } 714 }
713 ; CHECK: icmpUle64Bool: 715 ; CHECK: icmpUle64Bool:
714 ; CHECK: cmp 716 ; CHECK: cmp
715 ; CHECK: jb 717 ; CHECK: jb
716 ; CHECK: ja 718 ; CHECK: ja
717 ; CHECK: cmp 719 ; CHECK: cmp
718 ; CHECK: jbe 720 ; CHECK: jbe
719 721
720 define internal i64 @load64(i32 %a) { 722 define internal i64 @load64(i32 %a) {
721 entry: 723 entry:
722 %a.asptr = inttoptr i32 %a to i64* 724 %__1 = inttoptr i32 %a to i64*
723 %v0 = load i64* %a.asptr, align 1 725 %v0 = load i64* %__1, align 1
724 ret i64 %v0 726 ret i64 %v0
725 } 727 }
726 ; CHECK: load64: 728 ; CHECK: load64:
727 ; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp+4] 729 ; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp+4]
728 ; CHECK-NEXT: mov {{.*}}, dword ptr [e[[REGISTER]]] 730 ; CHECK-NEXT: mov {{.*}}, dword ptr [e[[REGISTER]]]
729 ; CHECK-NEXT: mov {{.*}}, dword ptr [e[[REGISTER]]+4] 731 ; CHECK-NEXT: mov {{.*}}, dword ptr [e[[REGISTER]]+4]
730 732
731 define internal void @store64(i32 %a, i64 %value) { 733 define internal void @store64(i32 %a, i64 %value) {
732 entry: 734 entry:
733 %a.asptr = inttoptr i32 %a to i64* 735 %__2 = inttoptr i32 %a to i64*
734 store i64 %value, i64* %a.asptr, align 1 736 store i64 %value, i64* %__2, align 1
735 ret void 737 ret void
736 } 738 }
737 ; CHECK: store64: 739 ; CHECK: store64:
738 ; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp+4] 740 ; CHECK: mov e[[REGISTER:[a-z]+]], dword ptr [esp+4]
739 ; CHECK: mov dword ptr [e[[REGISTER]]+4], 741 ; CHECK: mov dword ptr [e[[REGISTER]]+4],
740 ; CHECK: mov dword ptr [e[[REGISTER]]], 742 ; CHECK: mov dword ptr [e[[REGISTER]]],
741 743
742 define internal void @store64Const(i32 %a) { 744 define internal void @store64Const(i32 %a) {
743 entry: 745 entry:
744 %a.asptr = inttoptr i32 %a to i64* 746 %a.asptr = inttoptr i32 %a to i64*
(...skipping 45 matching lines...) Expand 10 before | Expand all | Expand 10 after
790 ; CHECK: cmp 792 ; CHECK: cmp
791 ; CHECK: jb 793 ; CHECK: jb
792 ; CHECK: ja 794 ; CHECK: ja
793 ; CHECK: cmp 795 ; CHECK: cmp
794 ; CHECK: jb 796 ; CHECK: jb
795 ; CHECK: cmp 797 ; CHECK: cmp
796 ; CHECK: jne 798 ; CHECK: jne
797 799
798 ; ERRORS-NOT: ICE translation error 800 ; ERRORS-NOT: ICE translation error
799 ; DUMP-NOT: SZ 801 ; DUMP-NOT: SZ
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