[arm][turbofan] Use NEON for unaligned float64 memory accesses

src/compiler/arm/code-generator-arm.cc

Index: src/compiler/arm/code-generator-arm.cc
diff --git a/src/compiler/arm/code-generator-arm.cc b/src/compiler/arm/code-generator-arm.cc
index 8f53d9901c6e4a2bb2bc268ceb1bb2128a5117a3..54698e717469b5df6594c7b2c51ecbf8ec34a4fe 100644
--- a/src/compiler/arm/code-generator-arm.cc
+++ b/src/compiler/arm/code-generator-arm.cc
@@ -1443,6 +1443,18 @@ CodeGenerator::CodeGenResult CodeGenerator::AssembleArchInstruction(
       __ vstr(i.InputFloatRegister(0), i.InputOffset(1));
       DCHECK_EQ(LeaveCC, i.OutputSBit());
       break;
+    case kArmVld1F64: {
+      MemOperand src = i.InputOffset();
+      __ vld1(NeonSize::Neon8, NeonListOperand(i.OutputDoubleRegister()),
+              NeonMemOperand(src.rn(), src.rm()));

[martyn.capewell, 2017/03/23 11:11:53]

I don't think this works, as the addressing mode that accepts two registers uses
the second register as a post index (ie. *rn; rn += rm) not an offset (ie. *(rn
+ rm)).

It will need either an address calculation in a scratch here, or emitting an
extra addition in the selector. Store will be similar.

+      break;
+    }
+    case kArmVst1F64: {
+      MemOperand src = i.InputOffset(1);
+      __ vst1(Neon8, NeonListOperand(i.InputDoubleRegister(0)),
+              NeonMemOperand(src.rn(), src.rm()));
+      break;
+    }
     case kArmVldrF64:
       __ vldr(i.OutputDoubleRegister(), i.InputOffset());
       DCHECK_EQ(LeaveCC, i.OutputSBit());