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Issue 2769403002: MIPS64: Fix code generator and simulator for DEXTM. (Closed)
Patch Set: Created 3 years, 9 months ago
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1 // Copyright 2011 the V8 project authors. All rights reserved. 1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include <limits.h> 5 #include <limits.h>
6 #include <stdarg.h> 6 #include <stdarg.h>
7 #include <stdlib.h> 7 #include <stdlib.h>
8 #include <cmath> 8 #include <cmath>
9 9
10 #if V8_TARGET_ARCH_MIPS64 10 #if V8_TARGET_ARCH_MIPS64
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4065 alu_out = static_cast<int32_t>((rs_u() & (mask << lsb)) >> lsb); 4065 alu_out = static_cast<int32_t>((rs_u() & (mask << lsb)) >> lsb);
4066 SetResult(rt_reg(), alu_out); 4066 SetResult(rt_reg(), alu_out);
4067 break; 4067 break;
4068 } 4068 }
4069 case DEXT: { // Mips64r2 instruction. 4069 case DEXT: { // Mips64r2 instruction.
4070 // Interpret rd field as 5-bit msb of extract. 4070 // Interpret rd field as 5-bit msb of extract.
4071 uint16_t msb = rd_reg(); 4071 uint16_t msb = rd_reg();
4072 // Interpret sa field as 5-bit lsb of extract. 4072 // Interpret sa field as 5-bit lsb of extract.
4073 uint16_t lsb = sa(); 4073 uint16_t lsb = sa();
4074 uint16_t size = msb + 1; 4074 uint16_t size = msb + 1;
4075 uint64_t mask = (1ULL << size) - 1; 4075 uint64_t mask = (size == 64) ? UINT64_MAX : (1ULL << size) - 1;
4076 alu_out = static_cast<int64_t>((rs_u() & (mask << lsb)) >> lsb); 4076 alu_out = static_cast<int64_t>((rs_u() & (mask << lsb)) >> lsb);
4077 SetResult(rt_reg(), alu_out); 4077 SetResult(rt_reg(), alu_out);
4078 break; 4078 break;
4079 } 4079 }
4080 case DEXTM: { 4080 case DEXTM: {
4081 // Interpret rd field as 5-bit msb of extract. 4081 // Interpret rd field as 5-bit msb of extract.
4082 uint16_t msb = rd_reg(); 4082 uint16_t msb = rd_reg();
4083 // Interpret sa field as 5-bit lsb of extract. 4083 // Interpret sa field as 5-bit lsb of extract.
4084 uint16_t lsb = sa(); 4084 uint16_t lsb = sa();
4085 uint16_t size = msb + 33; 4085 uint16_t size = msb + 33;
4086 uint64_t mask = (1ULL << size) - 1; 4086 uint64_t mask = (size == 64) ? UINT64_MAX : (1ULL << size) - 1;
4087 alu_out = static_cast<int64_t>((rs_u() & (mask << lsb)) >> lsb); 4087 alu_out = static_cast<int64_t>((rs_u() & (mask << lsb)) >> lsb);
4088 SetResult(rt_reg(), alu_out); 4088 SetResult(rt_reg(), alu_out);
4089 break; 4089 break;
4090 } 4090 }
4091 case DEXTU: { 4091 case DEXTU: {
4092 // Interpret rd field as 5-bit msb of extract. 4092 // Interpret rd field as 5-bit msb of extract.
4093 uint16_t msb = rd_reg(); 4093 uint16_t msb = rd_reg();
4094 // Interpret sa field as 5-bit lsb of extract. 4094 // Interpret sa field as 5-bit lsb of extract.
4095 uint16_t lsb = sa() + 32; 4095 uint16_t lsb = sa() + 32;
4096 uint16_t size = msb + 1; 4096 uint16_t size = msb + 1;
4097 uint64_t mask = (1ULL << size) - 1; 4097 uint64_t mask = (size == 64) ? UINT64_MAX : (1ULL << size) - 1;
4098 alu_out = static_cast<int64_t>((rs_u() & (mask << lsb)) >> lsb); 4098 alu_out = static_cast<int64_t>((rs_u() & (mask << lsb)) >> lsb);
4099 SetResult(rt_reg(), alu_out); 4099 SetResult(rt_reg(), alu_out);
4100 break; 4100 break;
4101 } 4101 }
4102 case BSHFL: { 4102 case BSHFL: {
4103 int32_t sa = instr_.SaFieldRaw() >> kSaShift; 4103 int32_t sa = instr_.SaFieldRaw() >> kSaShift;
4104 switch (sa) { 4104 switch (sa) {
4105 case BITSWAP: { 4105 case BITSWAP: {
4106 uint32_t input = static_cast<uint32_t>(rt()); 4106 uint32_t input = static_cast<uint32_t>(rt());
4107 uint32_t output = 0; 4107 uint32_t output = 0;
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5143 } 5143 }
5144 5144
5145 5145
5146 #undef UNSUPPORTED 5146 #undef UNSUPPORTED
5147 } // namespace internal 5147 } // namespace internal
5148 } // namespace v8 5148 } // namespace v8
5149 5149
5150 #endif // USE_SIMULATOR 5150 #endif // USE_SIMULATOR
5151 5151
5152 #endif // V8_TARGET_ARCH_MIPS64 5152 #endif // V8_TARGET_ARCH_MIPS64
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