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1 // Copyright 2012 the V8 project authors. All rights reserved. | 1 // Copyright 2012 the V8 project authors. All rights reserved. |
2 // Use of this source code is governed by a BSD-style license that can be | 2 // Use of this source code is governed by a BSD-style license that can be |
3 // found in the LICENSE file. | 3 // found in the LICENSE file. |
4 | 4 |
5 // A Disassembler object is used to disassemble a block of code instruction by | 5 // A Disassembler object is used to disassemble a block of code instruction by |
6 // instruction. The default implementation of the NameConverter object can be | 6 // instruction. The default implementation of the NameConverter object can be |
7 // overriden to modify register names or to do symbol lookup on addresses. | 7 // overriden to modify register names or to do symbol lookup on addresses. |
8 // | 8 // |
9 // The example below will disassemble a block of code and print it to stdout. | 9 // The example below will disassemble a block of code and print it to stdout. |
10 // | 10 // |
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1466 break; | 1466 break; |
1467 } | 1467 } |
1468 case EXT: { | 1468 case EXT: { |
1469 Format(instr, "ext 'rt, 'rs, 'sa, 'ss1"); | 1469 Format(instr, "ext 'rt, 'rs, 'sa, 'ss1"); |
1470 break; | 1470 break; |
1471 } | 1471 } |
1472 case DEXT: { | 1472 case DEXT: { |
1473 Format(instr, "dext 'rt, 'rs, 'sa, 'ss1"); | 1473 Format(instr, "dext 'rt, 'rs, 'sa, 'ss1"); |
1474 break; | 1474 break; |
1475 } | 1475 } |
| 1476 case DEXTM: { |
| 1477 Format(instr, "dextm 'rt, 'rs, 'sa, 'ss1"); |
| 1478 break; |
| 1479 } |
| 1480 case DEXTU: { |
| 1481 Format(instr, "dextu 'rt, 'rs, 'sa, 'ss1"); |
| 1482 break; |
| 1483 } |
1476 case BSHFL: { | 1484 case BSHFL: { |
1477 int sa = instr->SaFieldRaw() >> kSaShift; | 1485 int sa = instr->SaFieldRaw() >> kSaShift; |
1478 switch (sa) { | 1486 switch (sa) { |
1479 case BITSWAP: { | 1487 case BITSWAP: { |
1480 Format(instr, "bitswap 'rd, 'rt"); | 1488 Format(instr, "bitswap 'rd, 'rt"); |
1481 break; | 1489 break; |
1482 } | 1490 } |
1483 case SEB: { | 1491 case SEB: { |
1484 Format(instr, "seb 'rd, 'rt"); | 1492 Format(instr, "seb 'rd, 'rt"); |
1485 break; | 1493 break; |
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2043 *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); | 2051 *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); |
2044 } | 2052 } |
2045 } | 2053 } |
2046 | 2054 |
2047 | 2055 |
2048 #undef UNSUPPORTED | 2056 #undef UNSUPPORTED |
2049 | 2057 |
2050 } // namespace disasm | 2058 } // namespace disasm |
2051 | 2059 |
2052 #endif // V8_TARGET_ARCH_MIPS64 | 2060 #endif // V8_TARGET_ARCH_MIPS64 |
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