[ARM] Make Simd 128 bit load/store more like existing load/store.

src/compiler/arm/instruction-selector-arm.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/base/adapters.h"
 #include "src/base/bits.h"
 #include "src/compiler/instruction-selector-impl.h"
 #include "src/compiler/node-matchers.h"
 #include "src/compiler/node-properties.h"
 
@@ skipping 409 matching lines @@
     case MachineRepresentation::kWord16:
       opcode = load_rep.IsUnsigned() ? kArmLdrh : kArmLdrsh;
       break;
     case MachineRepresentation::kTaggedSigned:   // Fall through.
     case MachineRepresentation::kTaggedPointer:  // Fall through.
     case MachineRepresentation::kTagged:  // Fall through.
     case MachineRepresentation::kWord32:
       opcode = kArmLdr;
       break;
     case MachineRepresentation::kSimd128:
-      opcode = kArmSimd128Load;
+      opcode = kArmVld1S128;
       break;
     case MachineRepresentation::kWord64:   // Fall through.
     case MachineRepresentation::kSimd1x4:  // Fall through.
     case MachineRepresentation::kSimd1x8:  // Fall through.
     case MachineRepresentation::kSimd1x16:  // Fall through.
     case MachineRepresentation::kNone:
       UNREACHABLE();
       return;
   }
 
@@ skipping 69 matching lines @@
       case MachineRepresentation::kWord16:
         opcode = kArmStrh;
         break;
       case MachineRepresentation::kTaggedSigned:   // Fall through.
       case MachineRepresentation::kTaggedPointer:  // Fall through.
       case MachineRepresentation::kTagged:  // Fall through.
       case MachineRepresentation::kWord32:
         opcode = kArmStr;
         break;
       case MachineRepresentation::kSimd128:
-        opcode = kArmSimd128Store;
+        opcode = kArmVst1S128;
         break;
       case MachineRepresentation::kWord64:   // Fall through.
       case MachineRepresentation::kSimd1x4:  // Fall through.
       case MachineRepresentation::kSimd1x8:  // Fall through.
       case MachineRepresentation::kSimd1x16:  // Fall through.
       case MachineRepresentation::kNone:
         UNREACHABLE();
         return;
     }
 
     InstructionOperand inputs[4];
     size_t input_count = 0;
     inputs[input_count++] = g.UseRegister(value);
     inputs[input_count++] = g.UseRegister(base);
     EmitStore(this, opcode, input_count, inputs, index);
   }
 }
 
 void InstructionSelector::VisitProtectedStore(Node* node) {
   // TODO(eholk)
   UNIMPLEMENTED();
 }
 
 void InstructionSelector::VisitUnalignedLoad(Node* node) {
-  UnalignedLoadRepresentation load_rep =
-      UnalignedLoadRepresentationOf(node->op());
+  MachineRepresentation load_rep =
+      UnalignedLoadRepresentationOf(node->op()).representation();
   ArmOperandGenerator g(this);
   Node* base = node->InputAt(0);
   Node* index = node->InputAt(1);
 
   InstructionCode opcode = kArmLdr;
   // Only floating point loads need to be specially handled; integer loads
   // support unaligned access. We support unaligned FP loads by loading to
-  // integer registers first, then moving to the destination FP register.
-  switch (load_rep.representation()) {
+  // integer registers first, then moving to the destination FP register. If
+  // NEON is supported, we use the vld1.8 instruction.
+  switch (load_rep) {
     case MachineRepresentation::kFloat32: {
       InstructionOperand temp = g.TempRegister();
       EmitLoad(this, opcode, &temp, base, index);
       Emit(kArmVmovF32U32, g.DefineAsRegister(node), temp);
       return;
     }
-    case MachineRepresentation::kFloat64: {
-      // Compute the address of the least-significant half of the FP value.
+    case MachineRepresentation::kFloat64:
+    case MachineRepresentation::kSimd128: {
+      // Compute the address of the least-significant byte of the FP value.
       // We assume that the base node is unlikely to be an encodable immediate
       // or the result of a shift operation, so only consider the addressing
       // mode that should be used for the index node.
       InstructionCode add_opcode = kArmAdd;
       InstructionOperand inputs[3];
       inputs[0] = g.UseRegister(base);
 
       size_t input_count;
       if (TryMatchImmediateOrShift(this, &add_opcode, index, &input_count,
                                    &inputs[1])) {
         // input_count has been set by TryMatchImmediateOrShift(), so
         // increment it to account for the base register in inputs[0].
         input_count++;
       } else {
         add_opcode |= AddressingModeField::encode(kMode_Operand2_R);
         inputs[1] = g.UseRegister(index);
         input_count = 2;  // Base register and index.
       }
 
       InstructionOperand addr = g.TempRegister();
       Emit(add_opcode, 1, &addr, input_count, inputs);
 
       if (CpuFeatures::IsSupported(NEON)) {
         // With NEON we can load directly from the calculated address.
-        Emit(kArmVld1F64, g.DefineAsRegister(node), addr);
+        ArchOpcode op = load_rep == MachineRepresentation::kFloat64
+                            ? kArmVld1F64
+                            : kArmVld1S128;
+        Emit(op, g.DefineAsRegister(node), addr);
       } else {
+        DCHECK_NE(MachineRepresentation::kSimd128, load_rep);
         // Load both halves and move to an FP register.
         InstructionOperand fp_lo = g.TempRegister();
         InstructionOperand fp_hi = g.TempRegister();
         opcode |= AddressingModeField::encode(kMode_Offset_RI);
         Emit(opcode, fp_lo, addr, g.TempImmediate(0));
         Emit(opcode, fp_hi, addr, g.TempImmediate(4));
         Emit(kArmVmovF64U32U32, g.DefineAsRegister(node), fp_lo, fp_hi);
       }
       return;
     }
@@ skipping 12 matching lines @@
 
   InstructionOperand inputs[4];
   size_t input_count = 0;
 
   UnalignedStoreRepresentation store_rep =
       UnalignedStoreRepresentationOf(node->op());
 
   // Only floating point stores need to be specially handled; integer stores
   // support unaligned access. We support unaligned FP stores by moving the
   // value to integer registers first, then storing to the destination address.
+  // If NEON is supported, we use the vst1.8 instruction.
   switch (store_rep) {
     case MachineRepresentation::kFloat32: {
       inputs[input_count++] = g.TempRegister();
       Emit(kArmVmovU32F32, inputs[0], g.UseRegister(value));
       inputs[input_count++] = g.UseRegister(base);
       EmitStore(this, kArmStr, input_count, inputs, index);
       return;
     }
-    case MachineRepresentation::kFloat64: {
+    case MachineRepresentation::kFloat64:
+    case MachineRepresentation::kSimd128: {
       if (CpuFeatures::IsSupported(NEON)) {
         InstructionOperand address = g.TempRegister();
         {
           // First we have to calculate the actual address.
           InstructionCode add_opcode = kArmAdd;
           InstructionOperand inputs[3];
           inputs[0] = g.UseRegister(base);
 
           size_t input_count;
           if (TryMatchImmediateOrShift(this, &add_opcode, index, &input_count,
                                        &inputs[1])) {
             // input_count has been set by TryMatchImmediateOrShift(), so
             // increment it to account for the base register in inputs[0].
             input_count++;
           } else {
             add_opcode |= AddressingModeField::encode(kMode_Operand2_R);
             inputs[1] = g.UseRegister(index);
             input_count = 2;  // Base register and index.
           }
 
           Emit(add_opcode, 1, &address, input_count, inputs);
         }
 
         inputs[input_count++] = g.UseRegister(value);
         inputs[input_count++] = address;
-        Emit(kArmVst1F64, 0, nullptr, input_count, inputs);
+        ArchOpcode op = store_rep == MachineRepresentation::kFloat64
+                            ? kArmVst1F64
+                            : kArmVst1S128;
+        Emit(op, 0, nullptr, input_count, inputs);
       } else {
+        DCHECK_NE(MachineRepresentation::kSimd128, store_rep);
         // Store a 64-bit floating point value using two 32-bit integer stores.
         // Computing the store address here would require three live temporary
         // registers (fp<63:32>, fp<31:0>, address), so compute base + 4 after
         // storing the least-significant half of the value.
 
         // First, move the 64-bit FP value into two temporary integer registers.
         InstructionOperand fp[] = {g.TempRegister(), g.TempRegister()};
         inputs[input_count++] = g.UseRegister(value);
         Emit(kArmVmovU32U32F64, arraysize(fp), fp, input_count, inputs);
 
@@ skipping 1836 matching lines @@
   Vector<MachineType> req_aligned = Vector<MachineType>::New(2);
   req_aligned[0] = MachineType::Float32();
   req_aligned[1] = MachineType::Float64();
   return MachineOperatorBuilder::AlignmentRequirements::
       SomeUnalignedAccessUnsupported(req_aligned, req_aligned);
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8