[MIPS] Modify LongBranch expansion to work with sandboxing

lib/Target/Mips/MipsMCInstLower.cpp

 //===-- MipsMCInstLower.cpp - Convert Mips MachineInstr to MCInst ---------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains code to lower Mips MachineInstrs to their corresponding
 // MCInst records.
 //
 //===----------------------------------------------------------------------===//
 #include "MipsMCInstLower.h"
 #include "MCTargetDesc/MipsBaseInfo.h"
 #include "MipsAsmPrinter.h"
 #include "MipsInstrInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
+// @LOCALMOD-START
+#include "llvm/MC/MCELFStreamer.h"
+#include "llvm/MC/MCSymbol.h"
+// @LOCALMOD-END
 #include "llvm/Target/Mangler.h"
 
 using namespace llvm;
 
 MipsMCInstLower::MipsMCInstLower(MipsAsmPrinter &asmprinter)
   : AsmPrinter(asmprinter) {}
 
 void MipsMCInstLower::Initialize(Mangler *M, MCContext *C) {
   Mang = M;
   Ctx = C;
@@ skipping 111 matching lines @@
   case MachineOperand::MO_ConstantPoolIndex:
   case MachineOperand::MO_BlockAddress:
     return LowerSymbolOperand(MO, MOTy, offset);
   case MachineOperand::MO_RegisterMask:
     break;
  }
 
   return MCOperand();
 }
 
+// @LOCALMOD-START
+
+// TempSymbol cannot be member of MipsMCInstLower since Lower methods are const.
+static MCSymbol *TempSymbol = NULL;
+
+void MipsMCInstLower::LowerNaClLongBranchLUi(const MachineInstr *MI,
+                                         MCInst &OutMI) const {
+  OutMI.setOpcode(Mips::LUi);
+
+  // Lower register operand.
+  MCOperand Reg = LowerOperand(MI->getOperand(0));
+  if (Reg.isValid())
+    OutMI.addOperand(Reg);
+
+  // Create %hi($tgt-$baltgt). Since Mips backend currently doesn't support
+  // %hi(sym1-sym2) expressions, we first create temp symbol
+  // tmp = $tgt-$baltgt, and then create %hi(tmp) expression.
+  const MCSymbol *Symbol1 = MI->getOperand(1).getMBB()->getSymbol();
+  const MCSymbolRefExpr *MCSym1 = MCSymbolRefExpr::Create(Symbol1, *Ctx);
+  const MCSymbol *Symbol2 = MI->getOperand(2).getMBB()->getSymbol();
+  const MCSymbolRefExpr *MCSym2 = MCSymbolRefExpr::Create(Symbol2, *Ctx);
+
+  assert(TempSymbol == NULL);
+  TempSymbol = Ctx->CreateTempSymbol();
+  TempSymbol->setVariableValue(MCBinaryExpr::CreateSub(MCSym1, MCSym2, *Ctx));
+
+  const MCSymbolRefExpr *TempHi = MCSymbolRefExpr::Create(TempSymbol,
+      MCSymbolRefExpr::VK_Mips_ABS_HI, *Ctx);
+  OutMI.addOperand(MCOperand::CreateExpr(TempHi));
+
+  if (AsmPrinter.OutStreamer.hasRawTextSupport()) {
+    // For .s files, emit directive ".set $tmp, $tgt-$baltgt"
+    AsmPrinter.OutStreamer.EmitRawText(StringRef("\t.set\t")
+                                       + TempSymbol->getName()
+                                       + StringRef(", ")
+                                       + Symbol1->getName()
+                                       + StringRef("-")
+                                       + Symbol2->getName());
+  }
+}
+
+void MipsMCInstLower::LowerNaClLongBranchADDiu(const MachineInstr *MI,
+                                           MCInst &OutMI) const {
+  OutMI.setOpcode(Mips::ADDiu);
+
+  // Lower two register operands.
+  for (unsigned i = 0, e = 2; i != e; ++i) {
+    const MachineOperand &MO = MI->getOperand(i);
+    MCOperand Reg = LowerOperand(MO);
+
+    if (Reg.isValid())
+      OutMI.addOperand(Reg);
+  }
+
+  // Create %lo($tgt-$baltgt). See the comment above for %hi version.
+  assert(TempSymbol != NULL);
+  const MCSymbolRefExpr *TempLo = MCSymbolRefExpr::Create(TempSymbol,
+      MCSymbolRefExpr::VK_Mips_ABS_LO, *Ctx);
+  OutMI.addOperand(MCOperand::CreateExpr(TempLo));
+  TempSymbol = NULL;
+}
+// @LOCALMOD-END
+
 void MipsMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
+  // @LOCALMOD-START
+  if (MI->getOpcode() == Mips::NACL_LONG_BRANCH_LUi) {
+    LowerNaClLongBranchLUi(MI, OutMI);
+    return;
+  }
+  if (MI->getOpcode() == Mips::NACL_LONG_BRANCH_ADDiu) {
+    LowerNaClLongBranchADDiu(MI, OutMI);
+    return;
+  }
+  // @LOCALMOD-END
+
   OutMI.setOpcode(MI->getOpcode());
 
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = MI->getOperand(i);
     MCOperand MCOp = LowerOperand(MO);
 
     if (MCOp.isValid())
       OutMI.addOperand(MCOp);
   }
 }