[MIPS] Modify LongBranch expansion to work with sandboxing

lib/Target/Mips/MipsMCInstLower.cpp

 //===-- MipsMCInstLower.cpp - Convert Mips MachineInstr to MCInst ---------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains code to lower Mips MachineInstrs to their corresponding
@@ skipping 134 matching lines @@
   case MachineOperand::MO_ConstantPoolIndex:
   case MachineOperand::MO_BlockAddress:
     return LowerSymbolOperand(MO, MOTy, offset);
   case MachineOperand::MO_RegisterMask:
     break;
  }
 
   return MCOperand();
 }
 
+// @LOCALMOD-START
+void MipsMCInstLower::LowerLongBranchLUi(const MachineInstr *MI,
+                                         MCInst &OutMI) const {
+  OutMI.setOpcode(Mips::LUi);
+
+  // Lower register operand.
+  MCOperand Reg = LowerOperand(MI->getOperand(0));
+  if (Reg.isValid())
+    OutMI.addOperand(Reg);
+
+  // Lower branch target.
+  const MCSymbol *Symbol = MI->getOperand(1).getMBB()->getSymbol();
+  const MCSymbolRefExpr *MCSym
+    = MCSymbolRefExpr::Create(Symbol,
+                              MCSymbolRefExpr::VK_Mips_NACL_LONG_BRANCH_HI16,
+                              *Ctx);
+  MCOperand Br = MCOperand::CreateExpr(MCSym);
+  if (Br.isValid())
+    OutMI.addOperand(Br);
+}
+
+void MipsMCInstLower::LowerLongBranchADDiu(const MachineInstr *MI,
+                                           MCInst &OutMI) const {
+  OutMI.setOpcode(Mips::ADDiu);
+
+  // Lower two register operands.
+  for (unsigned i = 0, e = 2; i != e; ++i) {
+    const MachineOperand &MO = MI->getOperand(i);
+    MCOperand Reg = LowerOperand(MO);
+
+    if (Reg.isValid())
+      OutMI.addOperand(Reg);
+  }
+
+  // Lower branch target.
+  const MCSymbol *Symbol = MI->getOperand(2).getMBB()->getSymbol();
+  const MCSymbolRefExpr *MCSym
+    = MCSymbolRefExpr::Create(Symbol,
+                              MCSymbolRefExpr::VK_Mips_NACL_LONG_BRANCH_LO16,
+                              *Ctx);
+  MCOperand Br = MCOperand::CreateExpr(MCSym);
+  if (Br.isValid())
+    OutMI.addOperand(Br);
+}
+// @LOCALMOD-END
+
 void MipsMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
+  // @LOCALMOD-START
+  if (AsmPrinter.Subtarget->isTargetNaCl()) {
+    if (MI->getOpcode() == Mips::LUi
+        && (MI->getOperand(1).getTargetFlags()
+            == MipsII::MO_NACL_LONG_BRANCH)) {
+      LowerLongBranchLUi(MI, OutMI);
+      return;
+    }
+    if (MI->getOpcode() == Mips::ADDiu
+        && (MI->getOperand(2).getTargetFlags()
+            == MipsII::MO_NACL_LONG_BRANCH)) {
+      LowerLongBranchADDiu(MI, OutMI);
+      return;
+    }
+  }
+  // @LOCALMOD-END
+
   OutMI.setOpcode(MI->getOpcode());
 
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
     const MachineOperand &MO = MI->getOperand(i);
     MCOperand MCOp = LowerOperand(MO);
 
     if (MCOp.isValid())
       OutMI.addOperand(MCOp);
   }
 }