[MIPS] Modify LongBranch expansion to work with sandboxing

lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp

 //===-- MipsASMBackend.cpp - Mips Asm Backend  ----------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the MipsAsmBackend and MipsELFObjectWriter classes.
@@ skipping 59 matching lines @@
     Value = ((Value + 0x8000) >> 16) & 0xffff;
     break;
   case Mips::fixup_Mips_HIGHER:
     // Get the 3rd 16-bits.
     Value = ((Value + 0x80008000LL) >> 32) & 0xffff;
     break;
   case Mips::fixup_Mips_HIGHEST:
     // Get the 4th 16-bits.
     Value = ((Value + 0x800080008000LL) >> 48) & 0xffff;
     break;
+  // @LOCALMOD-START
+  case Mips::fixup_Mips_NACL_LONG_BRANCH_HI16:
+    // Resolve LUi part of the LUi/ADDiu long branch offset calculation.
+    // The Value is the offset of the target basic block from the LUi
+    // instruction. Since we need offset from the next instruction (ADDiu),
+    // we modify if by -4. Get the high 16-bits. Since the immediate from the
+    // ADDiu is treated as signed, add 1 if bit 15 is 1.
+    Value = ((Value - 4 + 0x8000) >> 16) & 0xffff;
+    break;
+  case Mips::fixup_Mips_NACL_LONG_BRANCH_LO16:
+    // Resolve ADDiu part of the LUi/ADDiu long branch offset calculation.
+    // Get the low 16-bits.
+    Value = Value & 0xffff;
+    break;
+  // @LOCALMOD-END
   }
 
   return Value;
 }
 
 namespace {
 class MipsAsmBackend : public MCAsmBackend {
   Triple::OSType OSType;
   bool IsLittle; // Big or little endian
   bool Is64Bit;  // 32 or 64 bit words
 
 public:
   MipsAsmBackend(const Target &T,  Triple::OSType _OSType,
                  bool _isLittle, bool _is64Bit)
     :MCAsmBackend(), OSType(_OSType), IsLittle(_isLittle), Is64Bit(_is64Bit) {}
 
   MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
     return createMipsELFObjectWriter(OS,
       MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit);
   }
 
+  /// processFixupValue - Target hook to process the literal value of a fixup
+  /// if necessary.
+  void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
+                         const MCFixup &Fixup, const MCFragment *DF,
+                         MCValue &Target, uint64_t &Value,
+                         bool &IsResolved) {
+    // @LOCALMOD-START

[Mark Seaborn, 2013/10/17 19:00:11]

This whole function should be inside LOCALMOD comments.

[petarj, 2013/10/22 23:10:27]

Done.

+    if (OSType == Triple::NaCl) {
+      if ((unsigned)Fixup.getKind() == Mips::fixup_Mips_NACL_LONG_BRANCH_HI16
+          || ((unsigned)Fixup.getKind()
+              == Mips::fixup_Mips_NACL_LONG_BRANCH_LO16))
+        // We don't need to emit relocation for long branch fixup.
+        IsResolved = true;

[Mark Seaborn, 2013/10/17 19:00:11]

Nit: Put {} brackets around this block since the condition is multi-line

[petarj, 2013/10/22 23:10:27]

Done.

+    }
+    // @LOCALMOD-END
+  }
+
   /// ApplyFixup - Apply the \p Value for given \p Fixup into the provided
   /// data fragment, at the offset specified by the fixup and following the
   /// fixup kind as appropriate.
   void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
                   uint64_t Value) const {
     MCFixupKind Kind = Fixup.getKind();
     Value = adjustFixupValue((unsigned)Kind, Value);
 
     if (!Value)
       return; // Doesn't change encoding.
@@ skipping 71 matching lines @@
       { "fixup_Mips_GPOFF_HI",     0,     16,   0 },
       { "fixup_Mips_GPOFF_LO",     0,     16,   0 },
       { "fixup_Mips_GOT_PAGE",     0,     16,   0 },
       { "fixup_Mips_GOT_OFST",     0,     16,   0 },
       { "fixup_Mips_GOT_DISP",     0,     16,   0 },
       { "fixup_Mips_HIGHER",       0,     16,   0 },
       { "fixup_Mips_HIGHEST",      0,     16,   0 },
       { "fixup_Mips_GOT_HI16",     0,     16,   0 },
       { "fixup_Mips_GOT_LO16",     0,     16,   0 },
       { "fixup_Mips_CALL_HI16",    0,     16,   0 },
-      { "fixup_Mips_CALL_LO16",    0,     16,   0 }
+      { "fixup_Mips_CALL_LO16",    0,     16,   0 },
+      // @LOCALMOD-START
+      { "fixup_Mips_NACL_LONG_BRANCH_HI16",    0,     16,
+        MCFixupKindInfo::FKF_IsPCRel },
+      { "fixup_Mips_NACL_LONG_BRANCH_LO16",    0,     16,
+        MCFixupKindInfo::FKF_IsPCRel }
+      // @LOCALMOD-END
     };
 
     if (Kind < FirstTargetFixupKind)
       return MCAsmBackend::getFixupKindInfo(Kind);
 
     assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
            "Invalid kind!");
     return Infos[Kind - FirstTargetFixupKind];
   }
 
@@ skipping 87 matching lines @@
   // @LOCALMOD-END
   return new MipsAsmBackend(T, Triple(TT).getOS(),
                             /*IsLittle*/true, /*Is64Bit*/true);
 }
 
 MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T, StringRef TT,
                                              StringRef CPU) {
   return new MipsAsmBackend(T, Triple(TT).getOS(),
                             /*IsLittle*/false, /*Is64Bit*/true);
 }