PPC: Clean up simulator code by introducing a OpcodeBase function

src/ppc/constants-ppc.h

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef V8_PPC_CONSTANTS_PPC_H_
 #define V8_PPC_CONSTANTS_PPC_H_
 
 #include <stdint.h>
 
 #include "src/base/logging.h"
@@ skipping 537 matching lines @@
   /* Vector Load Half Word into Half Word Odd Signed and Splat */              \
   V(evlhhossplat, EVLHHOSSPLAT, 0x1000030F)                                    \
   /* Vector Load Half Word into Half Word Odd Signed and Splat Indexed */      \
   V(evlhhossplatx, EVLHHOSSPLATX, 0x1000030E)                                  \
   /* Vector Load Half Word into Half Word Odd Unsigned and Splat */            \
   V(evlhhousplat, EVLHHOUSPLAT, 0x1000030D)                                    \
   /* Vector Load Half Word into Half Word Odd Unsigned and Splat Indexed */    \
   V(evlhhousplatx, EVLHHOUSPLATX, 0x1000030C)                                  \
   /* Vector Load Word into Two Half Words Even */                              \
   V(evlwhe, EVLWHE, 0x10000311)                                                \
-  /* Vector Load Word into Two Half Words Even Indexed */                      \
-  V(evlwhex, EVLWHEX, 0x10000310)                                              \
   /* Vector Load Word into Two Half Words Odd Signed (with sign extension) */  \
   V(evlwhos, EVLWHOS, 0x10000317)                                              \
   /* Vector Load Word into Two Half Words Odd Signed Indexed (with sign */     \
   /* extension) */                                                             \
   V(evlwhosx, EVLWHOSX, 0x10000316)                                            \
   /* Vector Load Word into Two Half Words Odd Unsigned (zero-extended) */      \
   V(evlwhou, EVLWHOU, 0x10000315)                                              \
   /* Vector Load Word into Two Half Words Odd Unsigned Indexed (zero- */       \
   /* extended) */                                                              \
   V(evlwhoux, EVLWHOUX, 0x10000314)                                            \
@@ skipping 755 matching lines @@
   /* Store Halfword with Decoration Indexed */                                 \
   V(sthdx, STHDX, 0x7C000546)                                                  \
   /* Store Word with Decoration Indexed */                                     \
   V(stwdx, STWDX, 0x7C000586)                                                  \
   /* Data Cache Block Allocate */                                              \
   V(dcba, DCBA, 0x7C0005EC)                                                    \
   /* Data Cache Block Invalidate */                                            \
   V(dcbi, DCBI, 0x7C0003AC)                                                    \
   /* Instruction Cache Block Touch */                                          \
   V(icbt, ICBT, 0x7C00002C)                                                    \
-  /* Memory Barrier */                                                         \
-  V(mbar, MBAR, 0x7C0006AC)                                                    \
   /* Move to Condition Register from XER */                                    \
   V(mcrxr, MCRXR, 0x7C000400)                                                  \
   /* TLB Invalidate Local Indexed */                                           \
   V(tlbilx, TLBILX, 0x7C000024)                                                \
   /* TLB Invalidate Virtual Address Indexed */                                 \
   V(tlbivax, TLBIVAX, 0x7C000624)                                              \
   /* TLB Read Entry */                                                         \
   V(tlbre, TLBRE, 0x7C000764)                                                  \
   /* TLB Search Indexed */                                                     \
   V(tlbsx, TLBSX, 0x7C000724)                                                  \
@@ skipping 330 matching lines @@
   V(std, STD, 0xF8000000)                                                      \
   /* Store Doubleword with Update */                                           \
   V(stdu, STDU, 0xF8000001)                                                    \
   /* Load Floating-Point Double Pair */                                        \
   V(lfdp, LFDP, 0xE4000000)                                                    \
   /* Store Floating-Point Double Pair */                                       \
   V(stfdp, STFDP, 0xF4000000)                                                  \
   /* Store Quadword */                                                         \
   V(stq, STQ, 0xF8000002)
 
+#define PPC_DQ_OPCODE_LIST(V)                                                  \
+  V(lsq, LSQ, 0xE0000000)
+
 #define PPC_D_OPCODE_LIST(V)                                                   \
   /* Trap Doubleword Immediate */                                              \
   V(tdi, TDI, 0x08000000)                                                      \
   /* Add Immediate */                                                          \
   V(addi, ADDI, 0x38000000)                                                    \
   /* Add Immediate Carrying */                                                 \
   V(addic, ADDIC, 0x30000000)                                                  \
   /* Add Immediate Carrying & record CR0 */                                    \
   V(addicx, ADDICx, 0x34000000)                                                \
   /* Add Immediate Shifted */                                                  \
@@ skipping 321 matching lines @@
   /* Subtract From & record OV */                                              \
   V(subfo, SUBFO, 0x7C000450)                                                  \
   /* Subtract From Zero Extended */                                            \
   V(subfze, SUBFZE, 0x7C000190)                                                \
   /* Subtract From Zero Extended & record OV */                                \
   V(subfzeo, SUBFZEO, 0x7C000590)                                              \
   /* Add and Generate Sixes */                                                 \
   V(addg, ADDG, 0x7C000094)                                                    \
   /* Multiply Accumulate Cross Halfword to Word Modulo Signed */               \
   V(macchw, MACCHW, 0x10000158)                                                \
-  /* Multiply Accumulate Cross Halfword to Word Modulo Signed & record OV */   \
-  V(macchwo, MACCHWO, 0x10000158)                                              \
   /* Multiply Accumulate Cross Halfword to Word Saturate Signed */             \
   V(macchws, MACCHWS, 0x100001D8)                                              \
-  /* Multiply Accumulate Cross Halfword to Word Saturate Signed & record */    \
-  /* OV */                                                                     \
-  V(macchwso, MACCHWSO, 0x100001D8)                                            \
   /* Multiply Accumulate Cross Halfword to Word Saturate Unsigned */           \
   V(macchwsu, MACCHWSU, 0x10000198)                                            \
-  /* Multiply Accumulate Cross Halfword to Word Saturate Unsigned & record */  \
-  /* OV */                                                                     \
-  V(macchwsuo, MACCHWSUO, 0x10000198)                                          \
   /* Multiply Accumulate Cross Halfword to Word Modulo Unsigned */             \
   V(macchwu, MACCHWU, 0x10000118)                                              \
-  /* Multiply Accumulate Cross Halfword to Word Modulo Unsigned & record */    \
-  /* OV */                                                                     \
-  V(macchwuo, MACCHWUO, 0x10000118)                                            \
   /* Multiply Accumulate High Halfword to Word Modulo Signed */                \
   V(machhw, MACHHW, 0x10000058)                                                \
-  /* Multiply Accumulate High Halfword to Word Modulo Signed & record OV */    \
-  V(machhwo, MACHHWO, 0x10000058)                                              \
   /* Multiply Accumulate High Halfword to Word Saturate Signed */              \
   V(machhws, MACHHWS, 0x100000D8)                                              \
-  /* Multiply Accumulate High Halfword to Word Saturate Signed & record OV */  \
-  V(machhwso, MACHHWSO, 0x100000D8)                                            \
   /* Multiply Accumulate High Halfword to Word Saturate Unsigned */            \
   V(machhwsu, MACHHWSU, 0x10000098)                                            \
-  /* Multiply Accumulate High Halfword to Word Saturate Unsigned & record */   \
-  /* OV */                                                                     \
-  V(machhwsuo, MACHHWSUO, 0x10000098)                                          \
   /* Multiply Accumulate High Halfword to Word Modulo Unsigned */              \
   V(machhwu, MACHHWU, 0x10000018)                                              \
-  /* Multiply Accumulate High Halfword to Word Modulo Unsigned & record OV */  \
-  V(machhwuo, MACHHWUO, 0x10000018)                                            \
   /* Multiply Accumulate Low Halfword to Word Modulo Signed */                 \
   V(maclhw, MACLHW, 0x10000358)                                                \
-  /* Multiply Accumulate Low Halfword to Word Modulo Signed & record OV */     \
-  V(maclhwo, MACLHWO, 0x10000358)                                              \
   /* Multiply Accumulate Low Halfword to Word Saturate Signed */               \
   V(maclhws, MACLHWS, 0x100003D8)                                              \
-  /* Multiply Accumulate Low Halfword to Word Saturate Signed & record OV */   \
-  V(maclhwso, MACLHWSO, 0x100003D8)                                            \
   /* Multiply Accumulate Low Halfword to Word Saturate Unsigned */             \
   V(maclhwsu, MACLHWSU, 0x10000398)                                            \
-  /* Multiply Accumulate Low Halfword to Word Saturate Unsigned & record */    \
-  /* OV */                                                                     \
-  V(maclhwsuo, MACLHWSUO, 0x10000398)                                          \
   /* Multiply Accumulate Low Halfword to Word Modulo Unsigned */               \
   V(maclhwu, MACLHWU, 0x10000318)                                              \
-  /* Multiply Accumulate Low Halfword to Word Modulo Unsigned & record OV */   \
-  V(maclhwuo, MACLHWUO, 0x10000318)                                            \
   /* Negative Multiply Accumulate Cross Halfword to Word Modulo Signed */      \
   V(nmacchw, NMACCHW, 0x1000015C)                                              \
-  /* Negative Multiply Accumulate Cross Halfword to Word Modulo Signed & */    \
-  /* record OV */                                                              \
-  V(nmacchwo, NMACCHWO, 0x1000015C)                                            \
   /* Negative Multiply Accumulate Cross Halfword to Word Saturate Signed */    \
   V(nmacchws, NMACCHWS, 0x100001DC)                                            \
-  /* Negative Multiply Accumulate Cross Halfword to Word Saturate Signed & */  \
-  /* record OV */                                                              \
-  V(nmacchwso, NMACCHWSO, 0x100001DC)                                          \
   /* Negative Multiply Accumulate High Halfword to Word Modulo Signed */       \
   V(nmachhw, NMACHHW, 0x1000005C)                                              \
-  /* Negative Multiply Accumulate High Halfword to Word Modulo Signed & */     \
-  /* record OV */                                                              \
-  V(nmachhwo, NMACHHWO, 0x1000005C)                                            \
   /* Negative Multiply Accumulate High Halfword to Word Saturate Signed */     \
   V(nmachhws, NMACHHWS, 0x100000DC)                                            \
-  /* Negative Multiply Accumulate High Halfword to Word Saturate Signed & */   \
-  /* record OV */                                                              \
-  V(nmachhwso, NMACHHWSO, 0x100000DC)                                          \
   /* Negative Multiply Accumulate Low Halfword to Word Modulo Signed */        \
   V(nmaclhw, NMACLHW, 0x1000035C)                                              \
-  /* Negative Multiply Accumulate Low Halfword to Word Modulo Signed & */      \
-  /* record OV */                                                              \
-  V(nmaclhwo, NMACLHWO, 0x1000035C)                                            \
   /* Negative Multiply Accumulate Low Halfword to Word Saturate Signed */      \
   V(nmaclhws, NMACLHWS, 0x100003DC)                                            \
-  /* Negative Multiply Accumulate Low Halfword to Word Saturate Signed & */    \
-  /* record OV */                                                              \
-  V(nmaclhwso, NMACLHWSO, 0x100003DC)
 
 #define PPC_XL_OPCODE_LIST(V)                                                  \
   /* Branch Conditional to Count Register */                                   \
   V(bcctr, BCCTRX, 0x4C000420)                                                 \
   /* Branch Conditional to Link Register */                                    \
   V(bclr, BCLRX, 0x4C000020)                                                   \
   /* Condition Register AND */                                                 \
   V(crand, CRAND, 0x4C000202)                                                  \
   /* Condition Register AND with Complement */                                 \
   V(crandc, CRANDC, 0x4C000102)                                                \
@@ skipping 412 matching lines @@
 
 #define PPC_SC_OPCODE_LIST(V)                                                  \
   /* System Call */                                                            \
   V(sc, SC, 0x44000002)
 
 
 #define PPC_OPCODE_LIST(V)    \
   PPC_X_OPCODE_LIST(V)        \
   PPC_XO_OPCODE_LIST(V)       \
   PPC_DS_OPCODE_LIST(V)       \
+  PPC_DQ_OPCODE_LIST(V)       \
   PPC_MDS_OPCODE_LIST(V)      \
   PPC_MD_OPCODE_LIST(V)       \
   PPC_XS_OPCODE_LIST(V)       \
   PPC_D_OPCODE_LIST(V)        \
   PPC_I_OPCODE_LIST(V)        \
   PPC_B_OPCODE_LIST(V)        \
   PPC_XL_OPCODE_LIST(V)       \
   PPC_A_OPCODE_LIST(V)        \
   PPC_XFX_OPCODE_LIST(V)      \
   PPC_M_OPCODE_LIST(V)        \
@@ skipping 259 matching lines @@
   inline int RSValue() const { return Bits(25, 21); }
   inline int RTValue() const { return Bits(25, 21); }
   inline int RAValue() const { return Bits(20, 16); }
   DECLARE_STATIC_ACCESSOR(RAValue);
   inline int RBValue() const { return Bits(15, 11); }
   DECLARE_STATIC_ACCESSOR(RBValue);
   inline int RCValue() const { return Bits(10, 6); }
   DECLARE_STATIC_ACCESSOR(RCValue);
 
   inline int OpcodeValue() const { return static_cast<Opcode>(Bits(31, 26)); }
-  inline Opcode OpcodeField() const {
+  inline uint32_t OpcodeField() const {
     return static_cast<Opcode>(BitField(31, 26));
   }
 
+#define OPCODE_CASES(name, opcode_name, opcode_value) \
+  case opcode_name:
+
+  inline Opcode OpcodeBase() const {
+    uint32_t opcode = OpcodeField();
+    uint32_t extcode = OpcodeField();
+    switch (opcode) {
+      PPC_D_OPCODE_LIST(OPCODE_CASES)
+      PPC_I_OPCODE_LIST(OPCODE_CASES)
+      PPC_B_OPCODE_LIST(OPCODE_CASES)
+      PPC_M_OPCODE_LIST(OPCODE_CASES)
+        return static_cast<Opcode>(opcode);
+    }
+
+    opcode = extcode | BitField(10, 0);
+    switch (opcode) {
+      PPC_VX_OPCODE_LIST(OPCODE_CASES)
+        return static_cast<Opcode>(opcode);
+    }
+    opcode = extcode | BitField(9, 0);
+    switch (opcode) {
+      PPC_VC_OPCODE_LIST(OPCODE_CASES)
+        return static_cast<Opcode>(opcode);
+    }
+    opcode = extcode | BitField(10, 1) | BitField(20, 20);
+    switch (opcode) {
+      PPC_XFX_OPCODE_LIST(OPCODE_CASES)
+        return static_cast<Opcode>(opcode);
+    }
+    opcode = extcode | BitField(10, 1);
+    switch (opcode) {
+      PPC_X_OPCODE_LIST(OPCODE_CASES)
+      PPC_XL_OPCODE_LIST(OPCODE_CASES)
+      PPC_XFL_OPCODE_LIST(OPCODE_CASES)
+      PPC_XX1_OPCODE_LIST(OPCODE_CASES)
+      PPC_XX2_OPCODE_LIST(OPCODE_CASES)
+      PPC_EVX_OPCODE_LIST(OPCODE_CASES)
+        return static_cast<Opcode>(opcode);
+    }
+    opcode = extcode | BitField(9, 1);
+    switch (opcode) {
+      PPC_XO_OPCODE_LIST(OPCODE_CASES)
+      PPC_Z22_OPCODE_LIST(OPCODE_CASES)
+        return static_cast<Opcode>(opcode);
+    }
+    opcode = extcode | BitField(10, 2);
+    switch (opcode) {
+      PPC_XS_OPCODE_LIST(OPCODE_CASES)
+        return static_cast<Opcode>(opcode);
+    }
+    opcode = extcode | BitField(10, 3);
+    switch (opcode) {
+      PPC_EVS_OPCODE_LIST(OPCODE_CASES)
+      PPC_XX3_OPCODE_LIST(OPCODE_CASES)
+        return static_cast<Opcode>(opcode);
+    }
+    opcode = extcode | BitField(8, 1);
+    switch (opcode) {
+      PPC_Z23_OPCODE_LIST(OPCODE_CASES)
+        return static_cast<Opcode>(opcode);
+     }
+    opcode = extcode | BitField(5, 0);
+    switch (opcode) {
+      PPC_VA_OPCODE_LIST(OPCODE_CASES)
+        return static_cast<Opcode>(opcode);
+    }
+    opcode = extcode | BitField(5, 1);
+    switch (opcode) {
+      PPC_A_OPCODE_LIST(OPCODE_CASES)
+        return static_cast<Opcode>(opcode);
+    }
+    opcode = extcode | BitField(4, 1);
+    switch (opcode) {
+      PPC_MDS_OPCODE_LIST(OPCODE_CASES)
+        return static_cast<Opcode>(opcode);
+    }
+    opcode = extcode | BitField(4, 2);
+    switch (opcode) {
+      PPC_MD_OPCODE_LIST(OPCODE_CASES)
+        return static_cast<Opcode>(opcode);
+    }
+    opcode = extcode | BitField(5, 4);
+    switch (opcode) {
+      PPC_XX4_OPCODE_LIST(OPCODE_CASES)
+        return static_cast<Opcode>(opcode);
+    }
+    opcode = extcode | BitField(2, 0);
+    switch (opcode) {
+      PPC_DQ_OPCODE_LIST(OPCODE_CASES)
+        return static_cast<Opcode>(opcode);
+    }
+    opcode = extcode | BitField(1, 0);
+    switch (opcode) {
+      PPC_DS_OPCODE_LIST(OPCODE_CASES)
+        return static_cast<Opcode>(opcode);
+    }
+    opcode = extcode | BitField(1, 1);
+    switch (opcode) {
+      PPC_SC_OPCODE_LIST(OPCODE_CASES)
+        return static_cast<Opcode>(opcode);
+    }
+printf("opcode = %x\n", InstructionBits());
+    UNIMPLEMENTED();
+    return static_cast<Opcode>(0);
+  }
+
+#undef OPCODE_CASES
+
   // Fields used in Software interrupt instructions
   inline SoftwareInterruptCodes SvcValue() const {
     return static_cast<SoftwareInterruptCodes>(Bits(23, 0));
   }
 
   // Instructions are read of out a code stream. The only way to get a
   // reference to an instruction is to convert a pointer. There is no way
   // to allocate or create instances of class Instruction.
   // Use the At(pc) function to create references to Instruction.
   static Instruction* At(byte* pc) {
@@ skipping 23 matching lines @@
   // Lookup the register number for the name provided.
   static int Number(const char* name);
 
  private:
   static const char* names_[kNumDoubleRegisters];
 };
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_PPC_CONSTANTS_PPC_H_