[arm64] Use acquire/release memory accesses for atomics

src/arm64/assembler-arm64.cc

Index: src/arm64/assembler-arm64.cc
diff --git a/src/arm64/assembler-arm64.cc b/src/arm64/assembler-arm64.cc
index 2b8f2ae64460974947cbf9f43cdc1dc7d4ff6127..ac6931dec76d3e95aa3f8ab86eb64f6faef9a857 100644
--- a/src/arm64/assembler-arm64.cc
+++ b/src/arm64/assembler-arm64.cc
@@ -1698,19 +1698,19 @@ void Assembler::ldr(const CPURegister& rt, const Immediate& imm) {
 void Assembler::ldar(const Register& rt, const Register& rn) {
   DCHECK(rn.Is64Bits());
   LoadStoreAcquireReleaseOp op = rt.Is32Bits() ? LDAR_w : LDAR_x;
-  Emit(op | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt));
+  Emit(op | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt));
 }
 
 void Assembler::ldaxr(const Register& rt, const Register& rn) {
   DCHECK(rn.Is64Bits());
   LoadStoreAcquireReleaseOp op = rt.Is32Bits() ? LDAXR_w : LDAXR_x;
-  Emit(op | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt));
+  Emit(op | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt));
 }
 
 void Assembler::stlr(const Register& rt, const Register& rn) {
   DCHECK(rn.Is64Bits());
   LoadStoreAcquireReleaseOp op = rt.Is32Bits() ? STLR_w : STLR_x;
-  Emit(op | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt));
+  Emit(op | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt));
 }
 
 void Assembler::stlxr(const Register& rs, const Register& rt,
@@ -1718,25 +1718,25 @@ void Assembler::stlxr(const Register& rs, const Register& rt,
   DCHECK(rs.Is32Bits());
   DCHECK(rn.Is64Bits());
   LoadStoreAcquireReleaseOp op = rt.Is32Bits() ? STLXR_w : STLXR_x;
-  Emit(op | Rs(rs) | Rt2(x31) | Rn(rn) | Rt(rt));
+  Emit(op | Rs(rs) | Rt2(x31) | RnSP(rn) | Rt(rt));
 }
 
 void Assembler::ldarb(const Register& rt, const Register& rn) {
   DCHECK(rt.Is32Bits());
   DCHECK(rn.Is64Bits());
-  Emit(LDAR_b | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt));
+  Emit(LDAR_b | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt));
 }
 
 void Assembler::ldaxrb(const Register& rt, const Register& rn) {
   DCHECK(rt.Is32Bits());
   DCHECK(rn.Is64Bits());
-  Emit(LDAXR_b | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt));
+  Emit(LDAXR_b | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt));
 }
 
 void Assembler::stlrb(const Register& rt, const Register& rn) {
   DCHECK(rt.Is32Bits());
   DCHECK(rn.Is64Bits());
-  Emit(STLR_b | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt));
+  Emit(STLR_b | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt));
 }
 
 void Assembler::stlxrb(const Register& rs, const Register& rt,
@@ -1744,25 +1744,25 @@ void Assembler::stlxrb(const Register& rs, const Register& rt,
   DCHECK(rs.Is32Bits());
   DCHECK(rt.Is32Bits());
   DCHECK(rn.Is64Bits());
-  Emit(STLXR_b | Rs(rs) | Rt2(x31) | Rn(rn) | Rt(rt));
+  Emit(STLXR_b | Rs(rs) | Rt2(x31) | RnSP(rn) | Rt(rt));
 }
 
 void Assembler::ldarh(const Register& rt, const Register& rn) {
   DCHECK(rt.Is32Bits());
   DCHECK(rn.Is64Bits());
-  Emit(LDAR_h | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt));
+  Emit(LDAR_h | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt));
 }
 
 void Assembler::ldaxrh(const Register& rt, const Register& rn) {
   DCHECK(rt.Is32Bits());
   DCHECK(rn.Is64Bits());
-  Emit(LDAXR_h | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt));
+  Emit(LDAXR_h | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt));
 }
 
 void Assembler::stlrh(const Register& rt, const Register& rn) {
   DCHECK(rt.Is32Bits());
   DCHECK(rn.Is64Bits());
-  Emit(STLR_h | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt));
+  Emit(STLR_h | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt));
 }
 
 void Assembler::stlxrh(const Register& rs, const Register& rt,
@@ -1770,7 +1770,7 @@ void Assembler::stlxrh(const Register& rs, const Register& rt,
   DCHECK(rs.Is32Bits());
   DCHECK(rt.Is32Bits());
   DCHECK(rn.Is64Bits());
-  Emit(STLXR_h | Rs(rs) | Rt2(x31) | Rn(rn) | Rt(rt));
+  Emit(STLXR_h | Rs(rs) | Rt2(x31) | RnSP(rn) | Rt(rt));
 }
 
 void Assembler::mov(const Register& rd, const Register& rm) {