[arm64] Use exclusive instructions in exchange

src/arm64/assembler-arm64.cc

Index: src/arm64/assembler-arm64.cc
diff --git a/src/arm64/assembler-arm64.cc b/src/arm64/assembler-arm64.cc
index 9ef115198a882c37e5da573077c04c739fa03a5a..3f12c6d167966140975d281555ae22e0aa450953 100644
--- a/src/arm64/assembler-arm64.cc
+++ b/src/arm64/assembler-arm64.cc
@@ -1694,22 +1694,57 @@ void Assembler::ldr(const CPURegister& rt, const Immediate& imm) {
   ldr_pcrel(rt, 0);
 }
 
+void Assembler::ldxrb(const Register& rt, const Register& rn) {
+  DCHECK(rn.Is64Bits());
+  Emit(LDXRB | RnSP(rn) | Rt(rt));
+}
+
+void Assembler::stxrb(const Register& rs, const Register& rt,
+                      const Register& rn) {
+  DCHECK(rn.Is64Bits());
+  Emit(STXRB | Rs(rs) | RnSP(rn) | Rt(rt));
+}
+
+void Assembler::ldxrh(const Register& rt, const Register& rn) {
+  DCHECK(rn.Is64Bits());
+  Emit(LDXRH | RnSP(rn) | Rt(rt));
+}
+
+void Assembler::stxrh(const Register& rs, const Register& rt,
+                      const Register& rn) {
+  DCHECK(rn.Is64Bits());
+  Emit(STXRH | Rs(rs) | RnSP(rn) | Rt(rt));
+}
+
+void Assembler::ldxr(const Register& rt, const Register& rn) {
+  DCHECK(rn.Is64Bits());
+  LoadStoreExclusiveOp op = rt.Is32Bits() ? LDXR_w : LDXR_x;
+  Emit(op | RnSP(rn) | Rt(rt));
+}
+
+void Assembler::stxr(const Register& rs, const Register& rt,
+                     const Register& rn) {
+  DCHECK(rn.Is64Bits());
+  LoadStoreExclusiveOp op = rt.Is32Bits() ? STXR_w : STXR_x;
+  Emit(op | Rs(rs) | RnSP(rn) | Rt(rt));
+}
+
 void Assembler::ldar(const Register& rt, const Register& rn) {
   DCHECK(rn.Is64Bits());
   LoadStoreAcquireReleaseOp op = rt.Is32Bits() ? LDAR_w : LDAR_x;
-  Emit(op | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt));
+  Emit(op | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt));
 }
 
 void Assembler::ldaxr(const Register& rt, const Register& rn) {
   DCHECK(rn.Is64Bits());
   LoadStoreAcquireReleaseOp op = rt.Is32Bits() ? LDAXR_w : LDAXR_x;
-  Emit(op | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt));
+  Emit(op | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt));
 }
 
 void Assembler::stlr(const Register& rt, const Register& rn) {
   DCHECK(rn.Is64Bits());
   LoadStoreAcquireReleaseOp op = rt.Is32Bits() ? STLR_w : STLR_x;
-  Emit(op | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt));
+  Emit(op | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt));
 }
 
 void Assembler::stlxr(const Register& rs, const Register& rt,
@@ -1717,25 +1752,25 @@ void Assembler::stlxr(const Register& rs, const Register& rt,
   DCHECK(rs.Is32Bits());
   DCHECK(rn.Is64Bits());
   LoadStoreAcquireReleaseOp op = rt.Is32Bits() ? STLXR_w : STLXR_x;
-  Emit(op | Rs(rs) | Rt2(x31) | Rn(rn) | Rt(rt));
+  Emit(op | Rs(rs) | Rt2(x31) | RnSP(rn) | Rt(rt));
 }
 
 void Assembler::ldarb(const Register& rt, const Register& rn) {
   DCHECK(rt.Is32Bits());
   DCHECK(rn.Is64Bits());
-  Emit(LDAR_b | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt));
+  Emit(LDAR_b | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt));
 }
 
 void Assembler::ldaxrb(const Register& rt, const Register& rn) {
   DCHECK(rt.Is32Bits());
   DCHECK(rn.Is64Bits());
-  Emit(LDAXR_b | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt));
+  Emit(LDAXR_b | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt));
 }
 
 void Assembler::stlrb(const Register& rt, const Register& rn) {
   DCHECK(rt.Is32Bits());
   DCHECK(rn.Is64Bits());
-  Emit(STLR_b | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt));
+  Emit(STLR_b | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt));
 }
 
 void Assembler::stlxrb(const Register& rs, const Register& rt,
@@ -1743,25 +1778,25 @@ void Assembler::stlxrb(const Register& rs, const Register& rt,
   DCHECK(rs.Is32Bits());
   DCHECK(rt.Is32Bits());
   DCHECK(rn.Is64Bits());
-  Emit(STLXR_b | Rs(rs) | Rt2(x31) | Rn(rn) | Rt(rt));
+  Emit(STLXR_b | Rs(rs) | Rt2(x31) | RnSP(rn) | Rt(rt));
 }
 
 void Assembler::ldarh(const Register& rt, const Register& rn) {
   DCHECK(rt.Is32Bits());
   DCHECK(rn.Is64Bits());
-  Emit(LDAR_h | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt));
+  Emit(LDAR_h | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt));
 }
 
 void Assembler::ldaxrh(const Register& rt, const Register& rn) {
   DCHECK(rt.Is32Bits());
   DCHECK(rn.Is64Bits());
-  Emit(LDAXR_h | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt));
+  Emit(LDAXR_h | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt));
 }
 
 void Assembler::stlrh(const Register& rt, const Register& rn) {
   DCHECK(rt.Is32Bits());
   DCHECK(rn.Is64Bits());
-  Emit(STLR_h | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt));
+  Emit(STLR_h | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt));
 }
 
 void Assembler::stlxrh(const Register& rs, const Register& rt,
@@ -1769,7 +1804,7 @@ void Assembler::stlxrh(const Register& rs, const Register& rt,
   DCHECK(rs.Is32Bits());
   DCHECK(rt.Is32Bits());
   DCHECK(rn.Is64Bits());
-  Emit(STLXR_h | Rs(rs) | Rt2(x31) | Rn(rn) | Rt(rt));
+  Emit(STLXR_h | Rs(rs) | Rt2(x31) | RnSP(rn) | Rt(rt));
 }
 
 void Assembler::mov(const Register& rd, const Register& rm) {