[arm64] Use exclusive instructions in exchange

src/arm64/simulator-arm64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <stdlib.h>
 #include <cmath>
 #include <cstdarg>
 
 #if V8_TARGET_ARCH_ARM64
 
@@ skipping 1934 matching lines @@
     case 2:
       return TransactionSize::HalfWord;
     case 4:
       return TransactionSize::Word;
     default:
       UNREACHABLE();
   }
   return TransactionSize::None;
 }
 
+void Simulator::VisitLoadStoreExclusive(Instruction* instr) {
+  unsigned rs = instr->Rs();
+  unsigned rt = instr->Rt();
+  unsigned rn = instr->Rn();
+  LoadStoreExclusiveOp op =
+      static_cast<LoadStoreExclusiveOp>(instr->Mask(LoadStoreExclusiveMask));
+  int32_t is_load = instr->LoadStoreXLoad();
+  unsigned access_size = 1 << instr->LoadStoreXSizeLog2();
+  uintptr_t address = LoadStoreAddress(rn, 0, AddrMode::Offset);
+  DCHECK_EQ(address % access_size, 0);
+  base::LockGuard<base::Mutex> lock_guard(&global_monitor_.Pointer()->mutex);
+  if (is_load != 0) {
+    local_monitor_.NotifyLoadExcl(address, get_transaction_size(access_size));
+    global_monitor_.Pointer()->NotifyLoadExcl_Locked(
+        address, &global_monitor_processor_);
+    switch (op) {
+      case LDXRB:
+        set_wreg_no_log(rt, MemoryRead<uint8_t>(address));
+        break;
+      case LDXRH:
+        set_wreg_no_log(rt, MemoryRead<uint16_t>(address));
+        break;
+      case LDXR_w:
+        set_wreg_no_log(rt, MemoryRead<uint32_t>(address));
+        break;
+      default:
+        UNIMPLEMENTED();
+    }
+    LogRead(address, access_size, rt);
+  } else {
+    if (local_monitor_.NotifyStoreExcl(address,
+                                       get_transaction_size(access_size)) &&
+        global_monitor_.Pointer()->NotifyStoreExcl_Locked(
+            address, &global_monitor_processor_)) {
+      switch (op) {
+        case STXRB:
+          MemoryWrite<uint8_t>(address, wreg(rt));
+          break;
+        case STXRH:
+          MemoryWrite<uint16_t>(address, wreg(rt));
+          break;
+        case STXR_w:
+          MemoryWrite<uint32_t>(address, wreg(rt));
+          break;
+        default:
+          UNIMPLEMENTED();
+      }
+      LogWrite(address, access_size, rt);
+      set_wreg(rs, 0);
+    } else {
+      set_wreg(rs, 1);
+    }
+  }
+}
+
 void Simulator::VisitLoadStoreAcquireRelease(Instruction* instr) {
   unsigned rs = instr->Rs();
   unsigned rt = instr->Rt();
   unsigned rn = instr->Rn();
   LoadStoreAcquireReleaseOp op = static_cast<LoadStoreAcquireReleaseOp>(
       instr->Mask(LoadStoreAcquireReleaseMask));
   int32_t is_acquire_release = instr->LoadStoreXAcquireRelease();
   int32_t is_not_exclusive = instr->LoadStoreXNotExclusive();
   int32_t is_load = instr->LoadStoreXLoad();
   int32_t is_pair = instr->LoadStoreXPair();
   DCHECK_NE(is_acquire_release, 0);
   DCHECK_EQ(is_not_exclusive, 0);  // Non exclusive unimplemented.
   DCHECK_EQ(is_pair, 0);           // Pair unimplemented.
   unsigned access_size = 1 << instr->LoadStoreXSizeLog2();
   uintptr_t address = LoadStoreAddress(rn, 0, AddrMode::Offset);
-  DCHECK(address % access_size == 0);
+  DCHECK_EQ(address % access_size, 0);
   base::LockGuard<base::Mutex> lock_guard(&global_monitor_.Pointer()->mutex);
   if (is_load != 0) {
     local_monitor_.NotifyLoadExcl(address, get_transaction_size(access_size));
     global_monitor_.Pointer()->NotifyLoadExcl_Locked(
         address, &global_monitor_processor_);
     switch (op) {
       case LDAXR_b:
         set_wreg_no_log(rt, MemoryRead<uint8_t>(address));
         break;
       case LDAXR_h:
@@ skipping 2179 matching lines @@
   processor->prev_ = nullptr;
   processor->next_ = nullptr;
 }
 
 #endif  // USE_SIMULATOR
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_TARGET_ARCH_ARM64