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1 // Copyright 2013 the V8 project authors. All rights reserved. | 1 // Copyright 2013 the V8 project authors. All rights reserved. |
2 // | 2 // |
3 // Redistribution and use in source and binary forms, with or without | 3 // Redistribution and use in source and binary forms, with or without |
4 // modification, are permitted provided that the following conditions are | 4 // modification, are permitted provided that the following conditions are |
5 // met: | 5 // met: |
6 // | 6 // |
7 // * Redistributions of source code must retain the above copyright | 7 // * Redistributions of source code must retain the above copyright |
8 // notice, this list of conditions and the following disclaimer. | 8 // notice, this list of conditions and the following disclaimer. |
9 // * Redistributions in binary form must reproduce the above | 9 // * Redistributions in binary form must reproduce the above |
10 // copyright notice, this list of conditions and the following | 10 // copyright notice, this list of conditions and the following |
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1687 // Currently we only support 64-bit literals. | 1687 // Currently we only support 64-bit literals. |
1688 DCHECK(rt.Is64Bits()); | 1688 DCHECK(rt.Is64Bits()); |
1689 | 1689 |
1690 RecordRelocInfo(imm.rmode(), imm.value()); | 1690 RecordRelocInfo(imm.rmode(), imm.value()); |
1691 BlockConstPoolFor(1); | 1691 BlockConstPoolFor(1); |
1692 // The load will be patched when the constpool is emitted, patching code | 1692 // The load will be patched when the constpool is emitted, patching code |
1693 // expect a load literal with offset 0. | 1693 // expect a load literal with offset 0. |
1694 ldr_pcrel(rt, 0); | 1694 ldr_pcrel(rt, 0); |
1695 } | 1695 } |
1696 | 1696 |
| 1697 void Assembler::ldxrb(const Register& rt, const Register& rn) { |
| 1698 DCHECK(rn.Is64Bits()); |
| 1699 Emit(LDXRB | RnSP(rn) | Rt(rt)); |
| 1700 } |
| 1701 |
| 1702 void Assembler::stxrb(const Register& rs, const Register& rt, |
| 1703 const Register& rn) { |
| 1704 DCHECK(rn.Is64Bits()); |
| 1705 Emit(STXRB | Rs(rs) | RnSP(rn) | Rt(rt)); |
| 1706 } |
| 1707 |
| 1708 void Assembler::ldxrh(const Register& rt, const Register& rn) { |
| 1709 DCHECK(rn.Is64Bits()); |
| 1710 Emit(LDXRH | RnSP(rn) | Rt(rt)); |
| 1711 } |
| 1712 |
| 1713 void Assembler::stxrh(const Register& rs, const Register& rt, |
| 1714 const Register& rn) { |
| 1715 DCHECK(rn.Is64Bits()); |
| 1716 Emit(STXRH | Rs(rs) | RnSP(rn) | Rt(rt)); |
| 1717 } |
| 1718 |
| 1719 void Assembler::ldxr(const Register& rt, const Register& rn) { |
| 1720 DCHECK(rn.Is64Bits()); |
| 1721 LoadStoreExclusiveOp op = rt.Is32Bits() ? LDXR_w : LDXR_x; |
| 1722 Emit(op | RnSP(rn) | Rt(rt)); |
| 1723 } |
| 1724 |
| 1725 void Assembler::stxr(const Register& rs, const Register& rt, |
| 1726 const Register& rn) { |
| 1727 DCHECK(rn.Is64Bits()); |
| 1728 LoadStoreExclusiveOp op = rt.Is32Bits() ? STXR_w : STXR_x; |
| 1729 Emit(op | Rs(rs) | RnSP(rn) | Rt(rt)); |
| 1730 } |
| 1731 |
1697 void Assembler::ldar(const Register& rt, const Register& rn) { | 1732 void Assembler::ldar(const Register& rt, const Register& rn) { |
1698 DCHECK(rn.Is64Bits()); | 1733 DCHECK(rn.Is64Bits()); |
1699 LoadStoreAcquireReleaseOp op = rt.Is32Bits() ? LDAR_w : LDAR_x; | 1734 LoadStoreAcquireReleaseOp op = rt.Is32Bits() ? LDAR_w : LDAR_x; |
1700 Emit(op | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt)); | 1735 Emit(op | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt)); |
1701 } | 1736 } |
1702 | 1737 |
1703 void Assembler::ldaxr(const Register& rt, const Register& rn) { | 1738 void Assembler::ldaxr(const Register& rt, const Register& rn) { |
1704 DCHECK(rn.Is64Bits()); | 1739 DCHECK(rn.Is64Bits()); |
1705 LoadStoreAcquireReleaseOp op = rt.Is32Bits() ? LDAXR_w : LDAXR_x; | 1740 LoadStoreAcquireReleaseOp op = rt.Is32Bits() ? LDAXR_w : LDAXR_x; |
1706 Emit(op | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt)); | 1741 Emit(op | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt)); |
1707 } | 1742 } |
1708 | 1743 |
1709 void Assembler::stlr(const Register& rt, const Register& rn) { | 1744 void Assembler::stlr(const Register& rt, const Register& rn) { |
1710 DCHECK(rn.Is64Bits()); | 1745 DCHECK(rn.Is64Bits()); |
1711 LoadStoreAcquireReleaseOp op = rt.Is32Bits() ? STLR_w : STLR_x; | 1746 LoadStoreAcquireReleaseOp op = rt.Is32Bits() ? STLR_w : STLR_x; |
1712 Emit(op | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt)); | 1747 Emit(op | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt)); |
1713 } | 1748 } |
1714 | 1749 |
1715 void Assembler::stlxr(const Register& rs, const Register& rt, | 1750 void Assembler::stlxr(const Register& rs, const Register& rt, |
1716 const Register& rn) { | 1751 const Register& rn) { |
1717 DCHECK(rs.Is32Bits()); | 1752 DCHECK(rs.Is32Bits()); |
1718 DCHECK(rn.Is64Bits()); | 1753 DCHECK(rn.Is64Bits()); |
1719 LoadStoreAcquireReleaseOp op = rt.Is32Bits() ? STLXR_w : STLXR_x; | 1754 LoadStoreAcquireReleaseOp op = rt.Is32Bits() ? STLXR_w : STLXR_x; |
1720 Emit(op | Rs(rs) | Rt2(x31) | Rn(rn) | Rt(rt)); | 1755 Emit(op | Rs(rs) | Rt2(x31) | RnSP(rn) | Rt(rt)); |
1721 } | 1756 } |
1722 | 1757 |
1723 void Assembler::ldarb(const Register& rt, const Register& rn) { | 1758 void Assembler::ldarb(const Register& rt, const Register& rn) { |
1724 DCHECK(rt.Is32Bits()); | 1759 DCHECK(rt.Is32Bits()); |
1725 DCHECK(rn.Is64Bits()); | 1760 DCHECK(rn.Is64Bits()); |
1726 Emit(LDAR_b | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt)); | 1761 Emit(LDAR_b | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt)); |
1727 } | 1762 } |
1728 | 1763 |
1729 void Assembler::ldaxrb(const Register& rt, const Register& rn) { | 1764 void Assembler::ldaxrb(const Register& rt, const Register& rn) { |
1730 DCHECK(rt.Is32Bits()); | 1765 DCHECK(rt.Is32Bits()); |
1731 DCHECK(rn.Is64Bits()); | 1766 DCHECK(rn.Is64Bits()); |
1732 Emit(LDAXR_b | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt)); | 1767 Emit(LDAXR_b | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt)); |
1733 } | 1768 } |
1734 | 1769 |
1735 void Assembler::stlrb(const Register& rt, const Register& rn) { | 1770 void Assembler::stlrb(const Register& rt, const Register& rn) { |
1736 DCHECK(rt.Is32Bits()); | 1771 DCHECK(rt.Is32Bits()); |
1737 DCHECK(rn.Is64Bits()); | 1772 DCHECK(rn.Is64Bits()); |
1738 Emit(STLR_b | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt)); | 1773 Emit(STLR_b | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt)); |
1739 } | 1774 } |
1740 | 1775 |
1741 void Assembler::stlxrb(const Register& rs, const Register& rt, | 1776 void Assembler::stlxrb(const Register& rs, const Register& rt, |
1742 const Register& rn) { | 1777 const Register& rn) { |
1743 DCHECK(rs.Is32Bits()); | 1778 DCHECK(rs.Is32Bits()); |
1744 DCHECK(rt.Is32Bits()); | 1779 DCHECK(rt.Is32Bits()); |
1745 DCHECK(rn.Is64Bits()); | 1780 DCHECK(rn.Is64Bits()); |
1746 Emit(STLXR_b | Rs(rs) | Rt2(x31) | Rn(rn) | Rt(rt)); | 1781 Emit(STLXR_b | Rs(rs) | Rt2(x31) | RnSP(rn) | Rt(rt)); |
1747 } | 1782 } |
1748 | 1783 |
1749 void Assembler::ldarh(const Register& rt, const Register& rn) { | 1784 void Assembler::ldarh(const Register& rt, const Register& rn) { |
1750 DCHECK(rt.Is32Bits()); | 1785 DCHECK(rt.Is32Bits()); |
1751 DCHECK(rn.Is64Bits()); | 1786 DCHECK(rn.Is64Bits()); |
1752 Emit(LDAR_h | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt)); | 1787 Emit(LDAR_h | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt)); |
1753 } | 1788 } |
1754 | 1789 |
1755 void Assembler::ldaxrh(const Register& rt, const Register& rn) { | 1790 void Assembler::ldaxrh(const Register& rt, const Register& rn) { |
1756 DCHECK(rt.Is32Bits()); | 1791 DCHECK(rt.Is32Bits()); |
1757 DCHECK(rn.Is64Bits()); | 1792 DCHECK(rn.Is64Bits()); |
1758 Emit(LDAXR_h | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt)); | 1793 Emit(LDAXR_h | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt)); |
1759 } | 1794 } |
1760 | 1795 |
1761 void Assembler::stlrh(const Register& rt, const Register& rn) { | 1796 void Assembler::stlrh(const Register& rt, const Register& rn) { |
1762 DCHECK(rt.Is32Bits()); | 1797 DCHECK(rt.Is32Bits()); |
1763 DCHECK(rn.Is64Bits()); | 1798 DCHECK(rn.Is64Bits()); |
1764 Emit(STLR_h | Rs(x31) | Rt2(x31) | Rn(rn) | Rt(rt)); | 1799 Emit(STLR_h | Rs(x31) | Rt2(x31) | RnSP(rn) | Rt(rt)); |
1765 } | 1800 } |
1766 | 1801 |
1767 void Assembler::stlxrh(const Register& rs, const Register& rt, | 1802 void Assembler::stlxrh(const Register& rs, const Register& rt, |
1768 const Register& rn) { | 1803 const Register& rn) { |
1769 DCHECK(rs.Is32Bits()); | 1804 DCHECK(rs.Is32Bits()); |
1770 DCHECK(rt.Is32Bits()); | 1805 DCHECK(rt.Is32Bits()); |
1771 DCHECK(rn.Is64Bits()); | 1806 DCHECK(rn.Is64Bits()); |
1772 Emit(STLXR_h | Rs(rs) | Rt2(x31) | Rn(rn) | Rt(rt)); | 1807 Emit(STLXR_h | Rs(rs) | Rt2(x31) | RnSP(rn) | Rt(rt)); |
1773 } | 1808 } |
1774 | 1809 |
1775 void Assembler::mov(const Register& rd, const Register& rm) { | 1810 void Assembler::mov(const Register& rd, const Register& rm) { |
1776 // Moves involving the stack pointer are encoded as add immediate with | 1811 // Moves involving the stack pointer are encoded as add immediate with |
1777 // second operand of zero. Otherwise, orr with first operand zr is | 1812 // second operand of zero. Otherwise, orr with first operand zr is |
1778 // used. | 1813 // used. |
1779 if (rd.IsSP() || rm.IsSP()) { | 1814 if (rd.IsSP() || rm.IsSP()) { |
1780 add(rd, rm, 0); | 1815 add(rd, rm, 0); |
1781 } else { | 1816 } else { |
1782 orr(rd, AppropriateZeroRegFor(rd), rm); | 1817 orr(rd, AppropriateZeroRegFor(rd), rm); |
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3217 movk(scratch, (target_offset >> 32) & 0xFFFF, 32); | 3252 movk(scratch, (target_offset >> 32) & 0xFFFF, 32); |
3218 DCHECK((target_offset >> 48) == 0); | 3253 DCHECK((target_offset >> 48) == 0); |
3219 add(rd, rd, scratch); | 3254 add(rd, rd, scratch); |
3220 } | 3255 } |
3221 | 3256 |
3222 | 3257 |
3223 } // namespace internal | 3258 } // namespace internal |
3224 } // namespace v8 | 3259 } // namespace v8 |
3225 | 3260 |
3226 #endif // V8_TARGET_ARCH_ARM64 | 3261 #endif // V8_TARGET_ARCH_ARM64 |
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