Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(475)

Side by Side Diff: src/v8globals.h

Issue 275433004: Require SSE2 support for the ia32 port. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 6 years, 7 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch | Annotate | Revision Log
« no previous file with comments | « src/runtime.cc ('k') | src/x64/assembler-x64.cc » ('j') | no next file with comments »
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #ifndef V8_V8GLOBALS_H_ 5 #ifndef V8_V8GLOBALS_H_
6 #define V8_V8GLOBALS_H_ 6 #define V8_V8GLOBALS_H_
7 7
8 #include "globals.h" 8 #include "globals.h"
9 #include "checks.h" 9 #include "checks.h"
10 10
(...skipping 385 matching lines...) Expand 10 before | Expand all | Expand 10 after
396 } 396 }
397 #else 397 #else
398 #define TRACK_MEMORY(name) 398 #define TRACK_MEMORY(name)
399 #endif 399 #endif
400 400
401 401
402 // Feature flags bit positions. They are mostly based on the CPUID spec. 402 // Feature flags bit positions. They are mostly based on the CPUID spec.
403 // On X86/X64, values below 32 are bits in EDX, values above 32 are bits in ECX. 403 // On X86/X64, values below 32 are bits in EDX, values above 32 are bits in ECX.
404 enum CpuFeature { SSE4_1 = 32 + 19, // x86 404 enum CpuFeature { SSE4_1 = 32 + 19, // x86
405 SSE3 = 32 + 0, // x86 405 SSE3 = 32 + 0, // x86
406 SSE2 = 26, // x86
407 CMOV = 15, // x86 406 CMOV = 15, // x86
408 VFP3 = 1, // ARM 407 VFP3 = 1, // ARM
409 ARMv7 = 2, // ARM 408 ARMv7 = 2, // ARM
410 SUDIV = 3, // ARM 409 SUDIV = 3, // ARM
411 UNALIGNED_ACCESSES = 4, // ARM 410 UNALIGNED_ACCESSES = 4, // ARM
412 MOVW_MOVT_IMMEDIATE_LOADS = 5, // ARM 411 MOVW_MOVT_IMMEDIATE_LOADS = 5, // ARM
413 VFP32DREGS = 6, // ARM 412 VFP32DREGS = 6, // ARM
414 NEON = 7, // ARM 413 NEON = 7, // ARM
415 SAHF = 0, // x86 414 SAHF = 0, // x86
416 FPU = 1}; // MIPS 415 FPU = 1}; // MIPS
(...skipping 128 matching lines...) Expand 10 before | Expand all | Expand 10 after
545 enum MinusZeroMode { 544 enum MinusZeroMode {
546 TREAT_MINUS_ZERO_AS_ZERO, 545 TREAT_MINUS_ZERO_AS_ZERO,
547 FAIL_ON_MINUS_ZERO 546 FAIL_ON_MINUS_ZERO
548 }; 547 };
549 548
550 } } // namespace v8::internal 549 } } // namespace v8::internal
551 550
552 namespace i = v8::internal; 551 namespace i = v8::internal;
553 552
554 #endif // V8_V8GLOBALS_H_ 553 #endif // V8_V8GLOBALS_H_
OLDNEW
« no previous file with comments | « src/runtime.cc ('k') | src/x64/assembler-x64.cc » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698