OLD | NEW |
1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions | 5 // modification, are permitted provided that the following conditions |
6 // are met: | 6 // are met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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55 uint64_t CpuFeatures::found_by_runtime_probing_only_ = 0; | 55 uint64_t CpuFeatures::found_by_runtime_probing_only_ = 0; |
56 uint64_t CpuFeatures::cross_compile_ = 0; | 56 uint64_t CpuFeatures::cross_compile_ = 0; |
57 | 57 |
58 | 58 |
59 ExternalReference ExternalReference::cpu_features() { | 59 ExternalReference ExternalReference::cpu_features() { |
60 ASSERT(CpuFeatures::initialized_); | 60 ASSERT(CpuFeatures::initialized_); |
61 return ExternalReference(&CpuFeatures::supported_); | 61 return ExternalReference(&CpuFeatures::supported_); |
62 } | 62 } |
63 | 63 |
64 | 64 |
65 int IntelDoubleRegister::NumAllocatableRegisters() { | 65 int DoubleRegister::NumAllocatableRegisters() { |
66 if (CpuFeatures::IsSupported(SSE2)) { | 66 return XMMRegister::kNumAllocatableRegisters; |
67 return XMMRegister::kNumAllocatableRegisters; | |
68 } else { | |
69 return X87Register::kNumAllocatableRegisters; | |
70 } | |
71 } | 67 } |
72 | 68 |
73 | 69 |
74 int IntelDoubleRegister::NumRegisters() { | 70 int DoubleRegister::NumRegisters() { |
75 if (CpuFeatures::IsSupported(SSE2)) { | 71 return XMMRegister::kNumRegisters; |
76 return XMMRegister::kNumRegisters; | |
77 } else { | |
78 return X87Register::kNumRegisters; | |
79 } | |
80 } | 72 } |
81 | 73 |
82 | 74 |
83 const char* IntelDoubleRegister::AllocationIndexToString(int index) { | 75 const char* DoubleRegister::AllocationIndexToString(int index) { |
84 if (CpuFeatures::IsSupported(SSE2)) { | 76 return XMMRegister::AllocationIndexToString(index); |
85 return XMMRegister::AllocationIndexToString(index); | |
86 } else { | |
87 return X87Register::AllocationIndexToString(index); | |
88 } | |
89 } | 77 } |
90 | 78 |
91 | 79 |
92 void CpuFeatures::Probe(bool serializer_enabled) { | 80 void CpuFeatures::Probe(bool serializer_enabled) { |
93 ASSERT(!initialized_); | 81 ASSERT(!initialized_); |
94 ASSERT(supported_ == 0); | 82 ASSERT(supported_ == 0); |
95 #ifdef DEBUG | 83 #ifdef DEBUG |
96 initialized_ = true; | 84 initialized_ = true; |
97 #endif | 85 #endif |
98 if (serializer_enabled) { | 86 if (serializer_enabled) { |
99 supported_ |= OS::CpuFeaturesImpliedByPlatform(); | 87 supported_ |= OS::CpuFeaturesImpliedByPlatform(); |
100 return; // No features if we might serialize. | 88 return; // No features if we might serialize. |
101 } | 89 } |
102 | 90 |
103 uint64_t probed_features = 0; | 91 uint64_t probed_features = 0; |
104 CPU cpu; | 92 CPU cpu; |
105 if (cpu.has_sse41()) { | 93 if (cpu.has_sse41()) { |
106 probed_features |= static_cast<uint64_t>(1) << SSE4_1; | 94 probed_features |= static_cast<uint64_t>(1) << SSE4_1; |
107 } | 95 } |
108 if (cpu.has_sse3()) { | 96 if (cpu.has_sse3()) { |
109 probed_features |= static_cast<uint64_t>(1) << SSE3; | 97 probed_features |= static_cast<uint64_t>(1) << SSE3; |
110 } | 98 } |
111 if (cpu.has_sse2()) { | 99 |
112 probed_features |= static_cast<uint64_t>(1) << SSE2; | 100 CHECK(cpu.has_sse2()); // SSE2 support is mandatory. |
113 } | 101 |
114 if (cpu.has_cmov()) { | 102 if (cpu.has_cmov()) { |
115 probed_features |= static_cast<uint64_t>(1) << CMOV; | 103 probed_features |= static_cast<uint64_t>(1) << CMOV; |
116 } | 104 } |
117 | 105 |
118 // SAHF must be available in compat/legacy mode. | 106 // SAHF must be available in compat/legacy mode. |
119 ASSERT(cpu.has_sahf()); | 107 ASSERT(cpu.has_sahf()); |
120 probed_features |= static_cast<uint64_t>(1) << SAHF; | 108 probed_features |= static_cast<uint64_t>(1) << SAHF; |
121 | 109 |
122 uint64_t platform_features = OS::CpuFeaturesImpliedByPlatform(); | 110 uint64_t platform_features = OS::CpuFeaturesImpliedByPlatform(); |
123 supported_ = probed_features | platform_features; | 111 supported_ = probed_features | platform_features; |
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342 while (*a == 0x66) a++; | 330 while (*a == 0x66) a++; |
343 if (*a == 0x90) return true; | 331 if (*a == 0x90) return true; |
344 if (a[0] == 0xf && a[1] == 0x1f) return true; | 332 if (a[0] == 0xf && a[1] == 0x1f) return true; |
345 return false; | 333 return false; |
346 } | 334 } |
347 | 335 |
348 | 336 |
349 void Assembler::Nop(int bytes) { | 337 void Assembler::Nop(int bytes) { |
350 EnsureSpace ensure_space(this); | 338 EnsureSpace ensure_space(this); |
351 | 339 |
352 if (!CpuFeatures::IsSupported(SSE2)) { | |
353 // Older CPUs that do not support SSE2 may not support multibyte NOP | |
354 // instructions. | |
355 for (; bytes > 0; bytes--) { | |
356 EMIT(0x90); | |
357 } | |
358 return; | |
359 } | |
360 | |
361 // Multi byte nops from http://support.amd.com/us/Processor_TechDocs/40546.pdf | 340 // Multi byte nops from http://support.amd.com/us/Processor_TechDocs/40546.pdf |
362 while (bytes > 0) { | 341 while (bytes > 0) { |
363 switch (bytes) { | 342 switch (bytes) { |
364 case 2: | 343 case 2: |
365 EMIT(0x66); | 344 EMIT(0x66); |
366 case 1: | 345 case 1: |
367 EMIT(0x90); | 346 EMIT(0x90); |
368 return; | 347 return; |
369 case 3: | 348 case 3: |
370 EMIT(0xf); | 349 EMIT(0xf); |
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1944 void Assembler::setcc(Condition cc, Register reg) { | 1923 void Assembler::setcc(Condition cc, Register reg) { |
1945 ASSERT(reg.is_byte_register()); | 1924 ASSERT(reg.is_byte_register()); |
1946 EnsureSpace ensure_space(this); | 1925 EnsureSpace ensure_space(this); |
1947 EMIT(0x0F); | 1926 EMIT(0x0F); |
1948 EMIT(0x90 | cc); | 1927 EMIT(0x90 | cc); |
1949 EMIT(0xC0 | reg.code()); | 1928 EMIT(0xC0 | reg.code()); |
1950 } | 1929 } |
1951 | 1930 |
1952 | 1931 |
1953 void Assembler::cvttss2si(Register dst, const Operand& src) { | 1932 void Assembler::cvttss2si(Register dst, const Operand& src) { |
1954 ASSERT(IsEnabled(SSE2)); | |
1955 EnsureSpace ensure_space(this); | 1933 EnsureSpace ensure_space(this); |
1956 EMIT(0xF3); | 1934 EMIT(0xF3); |
1957 EMIT(0x0F); | 1935 EMIT(0x0F); |
1958 EMIT(0x2C); | 1936 EMIT(0x2C); |
1959 emit_operand(dst, src); | 1937 emit_operand(dst, src); |
1960 } | 1938 } |
1961 | 1939 |
1962 | 1940 |
1963 void Assembler::cvttsd2si(Register dst, const Operand& src) { | 1941 void Assembler::cvttsd2si(Register dst, const Operand& src) { |
1964 ASSERT(IsEnabled(SSE2)); | |
1965 EnsureSpace ensure_space(this); | 1942 EnsureSpace ensure_space(this); |
1966 EMIT(0xF2); | 1943 EMIT(0xF2); |
1967 EMIT(0x0F); | 1944 EMIT(0x0F); |
1968 EMIT(0x2C); | 1945 EMIT(0x2C); |
1969 emit_operand(dst, src); | 1946 emit_operand(dst, src); |
1970 } | 1947 } |
1971 | 1948 |
1972 | 1949 |
1973 void Assembler::cvtsd2si(Register dst, XMMRegister src) { | 1950 void Assembler::cvtsd2si(Register dst, XMMRegister src) { |
1974 ASSERT(IsEnabled(SSE2)); | |
1975 EnsureSpace ensure_space(this); | 1951 EnsureSpace ensure_space(this); |
1976 EMIT(0xF2); | 1952 EMIT(0xF2); |
1977 EMIT(0x0F); | 1953 EMIT(0x0F); |
1978 EMIT(0x2D); | 1954 EMIT(0x2D); |
1979 emit_sse_operand(dst, src); | 1955 emit_sse_operand(dst, src); |
1980 } | 1956 } |
1981 | 1957 |
1982 | 1958 |
1983 void Assembler::cvtsi2sd(XMMRegister dst, const Operand& src) { | 1959 void Assembler::cvtsi2sd(XMMRegister dst, const Operand& src) { |
1984 ASSERT(IsEnabled(SSE2)); | |
1985 EnsureSpace ensure_space(this); | 1960 EnsureSpace ensure_space(this); |
1986 EMIT(0xF2); | 1961 EMIT(0xF2); |
1987 EMIT(0x0F); | 1962 EMIT(0x0F); |
1988 EMIT(0x2A); | 1963 EMIT(0x2A); |
1989 emit_sse_operand(dst, src); | 1964 emit_sse_operand(dst, src); |
1990 } | 1965 } |
1991 | 1966 |
1992 | 1967 |
1993 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) { | 1968 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) { |
1994 ASSERT(IsEnabled(SSE2)); | |
1995 EnsureSpace ensure_space(this); | 1969 EnsureSpace ensure_space(this); |
1996 EMIT(0xF3); | 1970 EMIT(0xF3); |
1997 EMIT(0x0F); | 1971 EMIT(0x0F); |
1998 EMIT(0x5A); | 1972 EMIT(0x5A); |
1999 emit_sse_operand(dst, src); | 1973 emit_sse_operand(dst, src); |
2000 } | 1974 } |
2001 | 1975 |
2002 | 1976 |
2003 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) { | 1977 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) { |
2004 ASSERT(IsEnabled(SSE2)); | |
2005 EnsureSpace ensure_space(this); | 1978 EnsureSpace ensure_space(this); |
2006 EMIT(0xF2); | 1979 EMIT(0xF2); |
2007 EMIT(0x0F); | 1980 EMIT(0x0F); |
2008 EMIT(0x5A); | 1981 EMIT(0x5A); |
2009 emit_sse_operand(dst, src); | 1982 emit_sse_operand(dst, src); |
2010 } | 1983 } |
2011 | 1984 |
2012 | 1985 |
2013 void Assembler::addsd(XMMRegister dst, XMMRegister src) { | 1986 void Assembler::addsd(XMMRegister dst, XMMRegister src) { |
2014 ASSERT(IsEnabled(SSE2)); | |
2015 EnsureSpace ensure_space(this); | 1987 EnsureSpace ensure_space(this); |
2016 EMIT(0xF2); | 1988 EMIT(0xF2); |
2017 EMIT(0x0F); | 1989 EMIT(0x0F); |
2018 EMIT(0x58); | 1990 EMIT(0x58); |
2019 emit_sse_operand(dst, src); | 1991 emit_sse_operand(dst, src); |
2020 } | 1992 } |
2021 | 1993 |
2022 | 1994 |
2023 void Assembler::addsd(XMMRegister dst, const Operand& src) { | 1995 void Assembler::addsd(XMMRegister dst, const Operand& src) { |
2024 ASSERT(IsEnabled(SSE2)); | |
2025 EnsureSpace ensure_space(this); | 1996 EnsureSpace ensure_space(this); |
2026 EMIT(0xF2); | 1997 EMIT(0xF2); |
2027 EMIT(0x0F); | 1998 EMIT(0x0F); |
2028 EMIT(0x58); | 1999 EMIT(0x58); |
2029 emit_sse_operand(dst, src); | 2000 emit_sse_operand(dst, src); |
2030 } | 2001 } |
2031 | 2002 |
2032 | 2003 |
2033 void Assembler::mulsd(XMMRegister dst, XMMRegister src) { | 2004 void Assembler::mulsd(XMMRegister dst, XMMRegister src) { |
2034 ASSERT(IsEnabled(SSE2)); | |
2035 EnsureSpace ensure_space(this); | 2005 EnsureSpace ensure_space(this); |
2036 EMIT(0xF2); | 2006 EMIT(0xF2); |
2037 EMIT(0x0F); | 2007 EMIT(0x0F); |
2038 EMIT(0x59); | 2008 EMIT(0x59); |
2039 emit_sse_operand(dst, src); | 2009 emit_sse_operand(dst, src); |
2040 } | 2010 } |
2041 | 2011 |
2042 | 2012 |
2043 void Assembler::mulsd(XMMRegister dst, const Operand& src) { | 2013 void Assembler::mulsd(XMMRegister dst, const Operand& src) { |
2044 ASSERT(IsEnabled(SSE2)); | |
2045 EnsureSpace ensure_space(this); | 2014 EnsureSpace ensure_space(this); |
2046 EMIT(0xF2); | 2015 EMIT(0xF2); |
2047 EMIT(0x0F); | 2016 EMIT(0x0F); |
2048 EMIT(0x59); | 2017 EMIT(0x59); |
2049 emit_sse_operand(dst, src); | 2018 emit_sse_operand(dst, src); |
2050 } | 2019 } |
2051 | 2020 |
2052 | 2021 |
2053 void Assembler::subsd(XMMRegister dst, XMMRegister src) { | 2022 void Assembler::subsd(XMMRegister dst, XMMRegister src) { |
2054 ASSERT(IsEnabled(SSE2)); | |
2055 EnsureSpace ensure_space(this); | 2023 EnsureSpace ensure_space(this); |
2056 EMIT(0xF2); | 2024 EMIT(0xF2); |
2057 EMIT(0x0F); | 2025 EMIT(0x0F); |
2058 EMIT(0x5C); | 2026 EMIT(0x5C); |
2059 emit_sse_operand(dst, src); | 2027 emit_sse_operand(dst, src); |
2060 } | 2028 } |
2061 | 2029 |
2062 | 2030 |
2063 void Assembler::divsd(XMMRegister dst, XMMRegister src) { | 2031 void Assembler::divsd(XMMRegister dst, XMMRegister src) { |
2064 ASSERT(IsEnabled(SSE2)); | |
2065 EnsureSpace ensure_space(this); | 2032 EnsureSpace ensure_space(this); |
2066 EMIT(0xF2); | 2033 EMIT(0xF2); |
2067 EMIT(0x0F); | 2034 EMIT(0x0F); |
2068 EMIT(0x5E); | 2035 EMIT(0x5E); |
2069 emit_sse_operand(dst, src); | 2036 emit_sse_operand(dst, src); |
2070 } | 2037 } |
2071 | 2038 |
2072 | 2039 |
2073 void Assembler::xorpd(XMMRegister dst, XMMRegister src) { | 2040 void Assembler::xorpd(XMMRegister dst, XMMRegister src) { |
2074 ASSERT(IsEnabled(SSE2)); | |
2075 EnsureSpace ensure_space(this); | 2041 EnsureSpace ensure_space(this); |
2076 EMIT(0x66); | 2042 EMIT(0x66); |
2077 EMIT(0x0F); | 2043 EMIT(0x0F); |
2078 EMIT(0x57); | 2044 EMIT(0x57); |
2079 emit_sse_operand(dst, src); | 2045 emit_sse_operand(dst, src); |
2080 } | 2046 } |
2081 | 2047 |
2082 | 2048 |
2083 void Assembler::andps(XMMRegister dst, const Operand& src) { | 2049 void Assembler::andps(XMMRegister dst, const Operand& src) { |
2084 ASSERT(IsEnabled(SSE2)); | |
2085 EnsureSpace ensure_space(this); | 2050 EnsureSpace ensure_space(this); |
2086 EMIT(0x0F); | 2051 EMIT(0x0F); |
2087 EMIT(0x54); | 2052 EMIT(0x54); |
2088 emit_sse_operand(dst, src); | 2053 emit_sse_operand(dst, src); |
2089 } | 2054 } |
2090 | 2055 |
2091 | 2056 |
2092 void Assembler::orps(XMMRegister dst, const Operand& src) { | 2057 void Assembler::orps(XMMRegister dst, const Operand& src) { |
2093 ASSERT(IsEnabled(SSE2)); | |
2094 EnsureSpace ensure_space(this); | 2058 EnsureSpace ensure_space(this); |
2095 EMIT(0x0F); | 2059 EMIT(0x0F); |
2096 EMIT(0x56); | 2060 EMIT(0x56); |
2097 emit_sse_operand(dst, src); | 2061 emit_sse_operand(dst, src); |
2098 } | 2062 } |
2099 | 2063 |
2100 | 2064 |
2101 void Assembler::xorps(XMMRegister dst, const Operand& src) { | 2065 void Assembler::xorps(XMMRegister dst, const Operand& src) { |
2102 ASSERT(IsEnabled(SSE2)); | |
2103 EnsureSpace ensure_space(this); | 2066 EnsureSpace ensure_space(this); |
2104 EMIT(0x0F); | 2067 EMIT(0x0F); |
2105 EMIT(0x57); | 2068 EMIT(0x57); |
2106 emit_sse_operand(dst, src); | 2069 emit_sse_operand(dst, src); |
2107 } | 2070 } |
2108 | 2071 |
2109 | 2072 |
2110 void Assembler::addps(XMMRegister dst, const Operand& src) { | 2073 void Assembler::addps(XMMRegister dst, const Operand& src) { |
2111 ASSERT(IsEnabled(SSE2)); | |
2112 EnsureSpace ensure_space(this); | 2074 EnsureSpace ensure_space(this); |
2113 EMIT(0x0F); | 2075 EMIT(0x0F); |
2114 EMIT(0x58); | 2076 EMIT(0x58); |
2115 emit_sse_operand(dst, src); | 2077 emit_sse_operand(dst, src); |
2116 } | 2078 } |
2117 | 2079 |
2118 | 2080 |
2119 void Assembler::subps(XMMRegister dst, const Operand& src) { | 2081 void Assembler::subps(XMMRegister dst, const Operand& src) { |
2120 ASSERT(IsEnabled(SSE2)); | |
2121 EnsureSpace ensure_space(this); | 2082 EnsureSpace ensure_space(this); |
2122 EMIT(0x0F); | 2083 EMIT(0x0F); |
2123 EMIT(0x5C); | 2084 EMIT(0x5C); |
2124 emit_sse_operand(dst, src); | 2085 emit_sse_operand(dst, src); |
2125 } | 2086 } |
2126 | 2087 |
2127 | 2088 |
2128 void Assembler::mulps(XMMRegister dst, const Operand& src) { | 2089 void Assembler::mulps(XMMRegister dst, const Operand& src) { |
2129 ASSERT(IsEnabled(SSE2)); | |
2130 EnsureSpace ensure_space(this); | 2090 EnsureSpace ensure_space(this); |
2131 EMIT(0x0F); | 2091 EMIT(0x0F); |
2132 EMIT(0x59); | 2092 EMIT(0x59); |
2133 emit_sse_operand(dst, src); | 2093 emit_sse_operand(dst, src); |
2134 } | 2094 } |
2135 | 2095 |
2136 | 2096 |
2137 void Assembler::divps(XMMRegister dst, const Operand& src) { | 2097 void Assembler::divps(XMMRegister dst, const Operand& src) { |
2138 ASSERT(IsEnabled(SSE2)); | |
2139 EnsureSpace ensure_space(this); | 2098 EnsureSpace ensure_space(this); |
2140 EMIT(0x0F); | 2099 EMIT(0x0F); |
2141 EMIT(0x5E); | 2100 EMIT(0x5E); |
2142 emit_sse_operand(dst, src); | 2101 emit_sse_operand(dst, src); |
2143 } | 2102 } |
2144 | 2103 |
2145 | 2104 |
2146 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { | 2105 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { |
2147 ASSERT(IsEnabled(SSE2)); | |
2148 EnsureSpace ensure_space(this); | 2106 EnsureSpace ensure_space(this); |
2149 EMIT(0xF2); | 2107 EMIT(0xF2); |
2150 EMIT(0x0F); | 2108 EMIT(0x0F); |
2151 EMIT(0x51); | 2109 EMIT(0x51); |
2152 emit_sse_operand(dst, src); | 2110 emit_sse_operand(dst, src); |
2153 } | 2111 } |
2154 | 2112 |
2155 | 2113 |
2156 void Assembler::andpd(XMMRegister dst, XMMRegister src) { | 2114 void Assembler::andpd(XMMRegister dst, XMMRegister src) { |
2157 ASSERT(IsEnabled(SSE2)); | |
2158 EnsureSpace ensure_space(this); | 2115 EnsureSpace ensure_space(this); |
2159 EMIT(0x66); | 2116 EMIT(0x66); |
2160 EMIT(0x0F); | 2117 EMIT(0x0F); |
2161 EMIT(0x54); | 2118 EMIT(0x54); |
2162 emit_sse_operand(dst, src); | 2119 emit_sse_operand(dst, src); |
2163 } | 2120 } |
2164 | 2121 |
2165 | 2122 |
2166 void Assembler::orpd(XMMRegister dst, XMMRegister src) { | 2123 void Assembler::orpd(XMMRegister dst, XMMRegister src) { |
2167 ASSERT(IsEnabled(SSE2)); | |
2168 EnsureSpace ensure_space(this); | 2124 EnsureSpace ensure_space(this); |
2169 EMIT(0x66); | 2125 EMIT(0x66); |
2170 EMIT(0x0F); | 2126 EMIT(0x0F); |
2171 EMIT(0x56); | 2127 EMIT(0x56); |
2172 emit_sse_operand(dst, src); | 2128 emit_sse_operand(dst, src); |
2173 } | 2129 } |
2174 | 2130 |
2175 | 2131 |
2176 void Assembler::ucomisd(XMMRegister dst, const Operand& src) { | 2132 void Assembler::ucomisd(XMMRegister dst, const Operand& src) { |
2177 ASSERT(IsEnabled(SSE2)); | |
2178 EnsureSpace ensure_space(this); | 2133 EnsureSpace ensure_space(this); |
2179 EMIT(0x66); | 2134 EMIT(0x66); |
2180 EMIT(0x0F); | 2135 EMIT(0x0F); |
2181 EMIT(0x2E); | 2136 EMIT(0x2E); |
2182 emit_sse_operand(dst, src); | 2137 emit_sse_operand(dst, src); |
2183 } | 2138 } |
2184 | 2139 |
2185 | 2140 |
2186 void Assembler::roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode) { | 2141 void Assembler::roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode) { |
2187 ASSERT(IsEnabled(SSE4_1)); | 2142 ASSERT(IsEnabled(SSE4_1)); |
2188 EnsureSpace ensure_space(this); | 2143 EnsureSpace ensure_space(this); |
2189 EMIT(0x66); | 2144 EMIT(0x66); |
2190 EMIT(0x0F); | 2145 EMIT(0x0F); |
2191 EMIT(0x3A); | 2146 EMIT(0x3A); |
2192 EMIT(0x0B); | 2147 EMIT(0x0B); |
2193 emit_sse_operand(dst, src); | 2148 emit_sse_operand(dst, src); |
2194 // Mask precision exeption. | 2149 // Mask precision exeption. |
2195 EMIT(static_cast<byte>(mode) | 0x8); | 2150 EMIT(static_cast<byte>(mode) | 0x8); |
2196 } | 2151 } |
2197 | 2152 |
2198 | 2153 |
2199 void Assembler::movmskpd(Register dst, XMMRegister src) { | 2154 void Assembler::movmskpd(Register dst, XMMRegister src) { |
2200 ASSERT(IsEnabled(SSE2)); | |
2201 EnsureSpace ensure_space(this); | 2155 EnsureSpace ensure_space(this); |
2202 EMIT(0x66); | 2156 EMIT(0x66); |
2203 EMIT(0x0F); | 2157 EMIT(0x0F); |
2204 EMIT(0x50); | 2158 EMIT(0x50); |
2205 emit_sse_operand(dst, src); | 2159 emit_sse_operand(dst, src); |
2206 } | 2160 } |
2207 | 2161 |
2208 | 2162 |
2209 void Assembler::movmskps(Register dst, XMMRegister src) { | 2163 void Assembler::movmskps(Register dst, XMMRegister src) { |
2210 ASSERT(IsEnabled(SSE2)); | |
2211 EnsureSpace ensure_space(this); | 2164 EnsureSpace ensure_space(this); |
2212 EMIT(0x0F); | 2165 EMIT(0x0F); |
2213 EMIT(0x50); | 2166 EMIT(0x50); |
2214 emit_sse_operand(dst, src); | 2167 emit_sse_operand(dst, src); |
2215 } | 2168 } |
2216 | 2169 |
2217 | 2170 |
2218 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) { | 2171 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) { |
2219 ASSERT(IsEnabled(SSE2)); | |
2220 EnsureSpace ensure_space(this); | 2172 EnsureSpace ensure_space(this); |
2221 EMIT(0x66); | 2173 EMIT(0x66); |
2222 EMIT(0x0F); | 2174 EMIT(0x0F); |
2223 EMIT(0x76); | 2175 EMIT(0x76); |
2224 emit_sse_operand(dst, src); | 2176 emit_sse_operand(dst, src); |
2225 } | 2177 } |
2226 | 2178 |
2227 | 2179 |
2228 void Assembler::cmpltsd(XMMRegister dst, XMMRegister src) { | 2180 void Assembler::cmpltsd(XMMRegister dst, XMMRegister src) { |
2229 ASSERT(IsEnabled(SSE2)); | |
2230 EnsureSpace ensure_space(this); | 2181 EnsureSpace ensure_space(this); |
2231 EMIT(0xF2); | 2182 EMIT(0xF2); |
2232 EMIT(0x0F); | 2183 EMIT(0x0F); |
2233 EMIT(0xC2); | 2184 EMIT(0xC2); |
2234 emit_sse_operand(dst, src); | 2185 emit_sse_operand(dst, src); |
2235 EMIT(1); // LT == 1 | 2186 EMIT(1); // LT == 1 |
2236 } | 2187 } |
2237 | 2188 |
2238 | 2189 |
2239 void Assembler::movaps(XMMRegister dst, XMMRegister src) { | 2190 void Assembler::movaps(XMMRegister dst, XMMRegister src) { |
2240 ASSERT(IsEnabled(SSE2)); | |
2241 EnsureSpace ensure_space(this); | 2191 EnsureSpace ensure_space(this); |
2242 EMIT(0x0F); | 2192 EMIT(0x0F); |
2243 EMIT(0x28); | 2193 EMIT(0x28); |
2244 emit_sse_operand(dst, src); | 2194 emit_sse_operand(dst, src); |
2245 } | 2195 } |
2246 | 2196 |
2247 | 2197 |
2248 void Assembler::shufps(XMMRegister dst, XMMRegister src, byte imm8) { | 2198 void Assembler::shufps(XMMRegister dst, XMMRegister src, byte imm8) { |
2249 ASSERT(IsEnabled(SSE2)); | |
2250 ASSERT(is_uint8(imm8)); | 2199 ASSERT(is_uint8(imm8)); |
2251 EnsureSpace ensure_space(this); | 2200 EnsureSpace ensure_space(this); |
2252 EMIT(0x0F); | 2201 EMIT(0x0F); |
2253 EMIT(0xC6); | 2202 EMIT(0xC6); |
2254 emit_sse_operand(dst, src); | 2203 emit_sse_operand(dst, src); |
2255 EMIT(imm8); | 2204 EMIT(imm8); |
2256 } | 2205 } |
2257 | 2206 |
2258 | 2207 |
2259 void Assembler::movdqa(const Operand& dst, XMMRegister src) { | 2208 void Assembler::movdqa(const Operand& dst, XMMRegister src) { |
2260 ASSERT(IsEnabled(SSE2)); | |
2261 EnsureSpace ensure_space(this); | 2209 EnsureSpace ensure_space(this); |
2262 EMIT(0x66); | 2210 EMIT(0x66); |
2263 EMIT(0x0F); | 2211 EMIT(0x0F); |
2264 EMIT(0x7F); | 2212 EMIT(0x7F); |
2265 emit_sse_operand(src, dst); | 2213 emit_sse_operand(src, dst); |
2266 } | 2214 } |
2267 | 2215 |
2268 | 2216 |
2269 void Assembler::movdqa(XMMRegister dst, const Operand& src) { | 2217 void Assembler::movdqa(XMMRegister dst, const Operand& src) { |
2270 ASSERT(IsEnabled(SSE2)); | |
2271 EnsureSpace ensure_space(this); | 2218 EnsureSpace ensure_space(this); |
2272 EMIT(0x66); | 2219 EMIT(0x66); |
2273 EMIT(0x0F); | 2220 EMIT(0x0F); |
2274 EMIT(0x6F); | 2221 EMIT(0x6F); |
2275 emit_sse_operand(dst, src); | 2222 emit_sse_operand(dst, src); |
2276 } | 2223 } |
2277 | 2224 |
2278 | 2225 |
2279 void Assembler::movdqu(const Operand& dst, XMMRegister src ) { | 2226 void Assembler::movdqu(const Operand& dst, XMMRegister src ) { |
2280 ASSERT(IsEnabled(SSE2)); | |
2281 EnsureSpace ensure_space(this); | 2227 EnsureSpace ensure_space(this); |
2282 EMIT(0xF3); | 2228 EMIT(0xF3); |
2283 EMIT(0x0F); | 2229 EMIT(0x0F); |
2284 EMIT(0x7F); | 2230 EMIT(0x7F); |
2285 emit_sse_operand(src, dst); | 2231 emit_sse_operand(src, dst); |
2286 } | 2232 } |
2287 | 2233 |
2288 | 2234 |
2289 void Assembler::movdqu(XMMRegister dst, const Operand& src) { | 2235 void Assembler::movdqu(XMMRegister dst, const Operand& src) { |
2290 ASSERT(IsEnabled(SSE2)); | |
2291 EnsureSpace ensure_space(this); | 2236 EnsureSpace ensure_space(this); |
2292 EMIT(0xF3); | 2237 EMIT(0xF3); |
2293 EMIT(0x0F); | 2238 EMIT(0x0F); |
2294 EMIT(0x6F); | 2239 EMIT(0x6F); |
2295 emit_sse_operand(dst, src); | 2240 emit_sse_operand(dst, src); |
2296 } | 2241 } |
2297 | 2242 |
2298 | 2243 |
2299 void Assembler::movntdqa(XMMRegister dst, const Operand& src) { | 2244 void Assembler::movntdqa(XMMRegister dst, const Operand& src) { |
2300 ASSERT(IsEnabled(SSE4_1)); | 2245 ASSERT(IsEnabled(SSE4_1)); |
2301 EnsureSpace ensure_space(this); | 2246 EnsureSpace ensure_space(this); |
2302 EMIT(0x66); | 2247 EMIT(0x66); |
2303 EMIT(0x0F); | 2248 EMIT(0x0F); |
2304 EMIT(0x38); | 2249 EMIT(0x38); |
2305 EMIT(0x2A); | 2250 EMIT(0x2A); |
2306 emit_sse_operand(dst, src); | 2251 emit_sse_operand(dst, src); |
2307 } | 2252 } |
2308 | 2253 |
2309 | 2254 |
2310 void Assembler::movntdq(const Operand& dst, XMMRegister src) { | 2255 void Assembler::movntdq(const Operand& dst, XMMRegister src) { |
2311 ASSERT(IsEnabled(SSE2)); | |
2312 EnsureSpace ensure_space(this); | 2256 EnsureSpace ensure_space(this); |
2313 EMIT(0x66); | 2257 EMIT(0x66); |
2314 EMIT(0x0F); | 2258 EMIT(0x0F); |
2315 EMIT(0xE7); | 2259 EMIT(0xE7); |
2316 emit_sse_operand(src, dst); | 2260 emit_sse_operand(src, dst); |
2317 } | 2261 } |
2318 | 2262 |
2319 | 2263 |
2320 void Assembler::prefetch(const Operand& src, int level) { | 2264 void Assembler::prefetch(const Operand& src, int level) { |
2321 ASSERT(is_uint2(level)); | 2265 ASSERT(is_uint2(level)); |
2322 EnsureSpace ensure_space(this); | 2266 EnsureSpace ensure_space(this); |
2323 EMIT(0x0F); | 2267 EMIT(0x0F); |
2324 EMIT(0x18); | 2268 EMIT(0x18); |
2325 // Emit hint number in Reg position of RegR/M. | 2269 // Emit hint number in Reg position of RegR/M. |
2326 XMMRegister code = XMMRegister::from_code(level); | 2270 XMMRegister code = XMMRegister::from_code(level); |
2327 emit_sse_operand(code, src); | 2271 emit_sse_operand(code, src); |
2328 } | 2272 } |
2329 | 2273 |
2330 | 2274 |
2331 void Assembler::movsd(const Operand& dst, XMMRegister src ) { | 2275 void Assembler::movsd(const Operand& dst, XMMRegister src ) { |
2332 ASSERT(IsEnabled(SSE2)); | |
2333 EnsureSpace ensure_space(this); | 2276 EnsureSpace ensure_space(this); |
2334 EMIT(0xF2); // double | 2277 EMIT(0xF2); // double |
2335 EMIT(0x0F); | 2278 EMIT(0x0F); |
2336 EMIT(0x11); // store | 2279 EMIT(0x11); // store |
2337 emit_sse_operand(src, dst); | 2280 emit_sse_operand(src, dst); |
2338 } | 2281 } |
2339 | 2282 |
2340 | 2283 |
2341 void Assembler::movsd(XMMRegister dst, const Operand& src) { | 2284 void Assembler::movsd(XMMRegister dst, const Operand& src) { |
2342 ASSERT(IsEnabled(SSE2)); | |
2343 EnsureSpace ensure_space(this); | 2285 EnsureSpace ensure_space(this); |
2344 EMIT(0xF2); // double | 2286 EMIT(0xF2); // double |
2345 EMIT(0x0F); | 2287 EMIT(0x0F); |
2346 EMIT(0x10); // load | 2288 EMIT(0x10); // load |
2347 emit_sse_operand(dst, src); | 2289 emit_sse_operand(dst, src); |
2348 } | 2290 } |
2349 | 2291 |
2350 | 2292 |
2351 void Assembler::movss(const Operand& dst, XMMRegister src ) { | 2293 void Assembler::movss(const Operand& dst, XMMRegister src ) { |
2352 ASSERT(IsEnabled(SSE2)); | |
2353 EnsureSpace ensure_space(this); | 2294 EnsureSpace ensure_space(this); |
2354 EMIT(0xF3); // float | 2295 EMIT(0xF3); // float |
2355 EMIT(0x0F); | 2296 EMIT(0x0F); |
2356 EMIT(0x11); // store | 2297 EMIT(0x11); // store |
2357 emit_sse_operand(src, dst); | 2298 emit_sse_operand(src, dst); |
2358 } | 2299 } |
2359 | 2300 |
2360 | 2301 |
2361 void Assembler::movss(XMMRegister dst, const Operand& src) { | 2302 void Assembler::movss(XMMRegister dst, const Operand& src) { |
2362 ASSERT(IsEnabled(SSE2)); | |
2363 EnsureSpace ensure_space(this); | 2303 EnsureSpace ensure_space(this); |
2364 EMIT(0xF3); // float | 2304 EMIT(0xF3); // float |
2365 EMIT(0x0F); | 2305 EMIT(0x0F); |
2366 EMIT(0x10); // load | 2306 EMIT(0x10); // load |
2367 emit_sse_operand(dst, src); | 2307 emit_sse_operand(dst, src); |
2368 } | 2308 } |
2369 | 2309 |
2370 | 2310 |
2371 void Assembler::movd(XMMRegister dst, const Operand& src) { | 2311 void Assembler::movd(XMMRegister dst, const Operand& src) { |
2372 ASSERT(IsEnabled(SSE2)); | |
2373 EnsureSpace ensure_space(this); | 2312 EnsureSpace ensure_space(this); |
2374 EMIT(0x66); | 2313 EMIT(0x66); |
2375 EMIT(0x0F); | 2314 EMIT(0x0F); |
2376 EMIT(0x6E); | 2315 EMIT(0x6E); |
2377 emit_sse_operand(dst, src); | 2316 emit_sse_operand(dst, src); |
2378 } | 2317 } |
2379 | 2318 |
2380 | 2319 |
2381 void Assembler::movd(const Operand& dst, XMMRegister src) { | 2320 void Assembler::movd(const Operand& dst, XMMRegister src) { |
2382 ASSERT(IsEnabled(SSE2)); | |
2383 EnsureSpace ensure_space(this); | 2321 EnsureSpace ensure_space(this); |
2384 EMIT(0x66); | 2322 EMIT(0x66); |
2385 EMIT(0x0F); | 2323 EMIT(0x0F); |
2386 EMIT(0x7E); | 2324 EMIT(0x7E); |
2387 emit_sse_operand(src, dst); | 2325 emit_sse_operand(src, dst); |
2388 } | 2326 } |
2389 | 2327 |
2390 | 2328 |
2391 void Assembler::extractps(Register dst, XMMRegister src, byte imm8) { | 2329 void Assembler::extractps(Register dst, XMMRegister src, byte imm8) { |
2392 ASSERT(IsEnabled(SSE4_1)); | 2330 ASSERT(IsEnabled(SSE4_1)); |
2393 ASSERT(is_uint8(imm8)); | 2331 ASSERT(is_uint8(imm8)); |
2394 EnsureSpace ensure_space(this); | 2332 EnsureSpace ensure_space(this); |
2395 EMIT(0x66); | 2333 EMIT(0x66); |
2396 EMIT(0x0F); | 2334 EMIT(0x0F); |
2397 EMIT(0x3A); | 2335 EMIT(0x3A); |
2398 EMIT(0x17); | 2336 EMIT(0x17); |
2399 emit_sse_operand(src, dst); | 2337 emit_sse_operand(src, dst); |
2400 EMIT(imm8); | 2338 EMIT(imm8); |
2401 } | 2339 } |
2402 | 2340 |
2403 | 2341 |
2404 void Assembler::pand(XMMRegister dst, XMMRegister src) { | 2342 void Assembler::pand(XMMRegister dst, XMMRegister src) { |
2405 ASSERT(IsEnabled(SSE2)); | |
2406 EnsureSpace ensure_space(this); | 2343 EnsureSpace ensure_space(this); |
2407 EMIT(0x66); | 2344 EMIT(0x66); |
2408 EMIT(0x0F); | 2345 EMIT(0x0F); |
2409 EMIT(0xDB); | 2346 EMIT(0xDB); |
2410 emit_sse_operand(dst, src); | 2347 emit_sse_operand(dst, src); |
2411 } | 2348 } |
2412 | 2349 |
2413 | 2350 |
2414 void Assembler::pxor(XMMRegister dst, XMMRegister src) { | 2351 void Assembler::pxor(XMMRegister dst, XMMRegister src) { |
2415 ASSERT(IsEnabled(SSE2)); | |
2416 EnsureSpace ensure_space(this); | 2352 EnsureSpace ensure_space(this); |
2417 EMIT(0x66); | 2353 EMIT(0x66); |
2418 EMIT(0x0F); | 2354 EMIT(0x0F); |
2419 EMIT(0xEF); | 2355 EMIT(0xEF); |
2420 emit_sse_operand(dst, src); | 2356 emit_sse_operand(dst, src); |
2421 } | 2357 } |
2422 | 2358 |
2423 | 2359 |
2424 void Assembler::por(XMMRegister dst, XMMRegister src) { | 2360 void Assembler::por(XMMRegister dst, XMMRegister src) { |
2425 ASSERT(IsEnabled(SSE2)); | |
2426 EnsureSpace ensure_space(this); | 2361 EnsureSpace ensure_space(this); |
2427 EMIT(0x66); | 2362 EMIT(0x66); |
2428 EMIT(0x0F); | 2363 EMIT(0x0F); |
2429 EMIT(0xEB); | 2364 EMIT(0xEB); |
2430 emit_sse_operand(dst, src); | 2365 emit_sse_operand(dst, src); |
2431 } | 2366 } |
2432 | 2367 |
2433 | 2368 |
2434 void Assembler::ptest(XMMRegister dst, XMMRegister src) { | 2369 void Assembler::ptest(XMMRegister dst, XMMRegister src) { |
2435 ASSERT(IsEnabled(SSE4_1)); | 2370 ASSERT(IsEnabled(SSE4_1)); |
2436 EnsureSpace ensure_space(this); | 2371 EnsureSpace ensure_space(this); |
2437 EMIT(0x66); | 2372 EMIT(0x66); |
2438 EMIT(0x0F); | 2373 EMIT(0x0F); |
2439 EMIT(0x38); | 2374 EMIT(0x38); |
2440 EMIT(0x17); | 2375 EMIT(0x17); |
2441 emit_sse_operand(dst, src); | 2376 emit_sse_operand(dst, src); |
2442 } | 2377 } |
2443 | 2378 |
2444 | 2379 |
2445 void Assembler::psllq(XMMRegister reg, int8_t shift) { | 2380 void Assembler::psllq(XMMRegister reg, int8_t shift) { |
2446 ASSERT(IsEnabled(SSE2)); | |
2447 EnsureSpace ensure_space(this); | 2381 EnsureSpace ensure_space(this); |
2448 EMIT(0x66); | 2382 EMIT(0x66); |
2449 EMIT(0x0F); | 2383 EMIT(0x0F); |
2450 EMIT(0x73); | 2384 EMIT(0x73); |
2451 emit_sse_operand(esi, reg); // esi == 6 | 2385 emit_sse_operand(esi, reg); // esi == 6 |
2452 EMIT(shift); | 2386 EMIT(shift); |
2453 } | 2387 } |
2454 | 2388 |
2455 | 2389 |
2456 void Assembler::psllq(XMMRegister dst, XMMRegister src) { | 2390 void Assembler::psllq(XMMRegister dst, XMMRegister src) { |
2457 ASSERT(IsEnabled(SSE2)); | |
2458 EnsureSpace ensure_space(this); | 2391 EnsureSpace ensure_space(this); |
2459 EMIT(0x66); | 2392 EMIT(0x66); |
2460 EMIT(0x0F); | 2393 EMIT(0x0F); |
2461 EMIT(0xF3); | 2394 EMIT(0xF3); |
2462 emit_sse_operand(dst, src); | 2395 emit_sse_operand(dst, src); |
2463 } | 2396 } |
2464 | 2397 |
2465 | 2398 |
2466 void Assembler::psrlq(XMMRegister reg, int8_t shift) { | 2399 void Assembler::psrlq(XMMRegister reg, int8_t shift) { |
2467 ASSERT(IsEnabled(SSE2)); | |
2468 EnsureSpace ensure_space(this); | 2400 EnsureSpace ensure_space(this); |
2469 EMIT(0x66); | 2401 EMIT(0x66); |
2470 EMIT(0x0F); | 2402 EMIT(0x0F); |
2471 EMIT(0x73); | 2403 EMIT(0x73); |
2472 emit_sse_operand(edx, reg); // edx == 2 | 2404 emit_sse_operand(edx, reg); // edx == 2 |
2473 EMIT(shift); | 2405 EMIT(shift); |
2474 } | 2406 } |
2475 | 2407 |
2476 | 2408 |
2477 void Assembler::psrlq(XMMRegister dst, XMMRegister src) { | 2409 void Assembler::psrlq(XMMRegister dst, XMMRegister src) { |
2478 ASSERT(IsEnabled(SSE2)); | |
2479 EnsureSpace ensure_space(this); | 2410 EnsureSpace ensure_space(this); |
2480 EMIT(0x66); | 2411 EMIT(0x66); |
2481 EMIT(0x0F); | 2412 EMIT(0x0F); |
2482 EMIT(0xD3); | 2413 EMIT(0xD3); |
2483 emit_sse_operand(dst, src); | 2414 emit_sse_operand(dst, src); |
2484 } | 2415 } |
2485 | 2416 |
2486 | 2417 |
2487 void Assembler::pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle) { | 2418 void Assembler::pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle) { |
2488 ASSERT(IsEnabled(SSE2)); | |
2489 EnsureSpace ensure_space(this); | 2419 EnsureSpace ensure_space(this); |
2490 EMIT(0x66); | 2420 EMIT(0x66); |
2491 EMIT(0x0F); | 2421 EMIT(0x0F); |
2492 EMIT(0x70); | 2422 EMIT(0x70); |
2493 emit_sse_operand(dst, src); | 2423 emit_sse_operand(dst, src); |
2494 EMIT(shuffle); | 2424 EMIT(shuffle); |
2495 } | 2425 } |
2496 | 2426 |
2497 | 2427 |
2498 void Assembler::pextrd(const Operand& dst, XMMRegister src, int8_t offset) { | 2428 void Assembler::pextrd(const Operand& dst, XMMRegister src, int8_t offset) { |
(...skipping 248 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
2747 fprintf(coverage_log, "%s\n", file_line); | 2677 fprintf(coverage_log, "%s\n", file_line); |
2748 fflush(coverage_log); | 2678 fflush(coverage_log); |
2749 } | 2679 } |
2750 } | 2680 } |
2751 | 2681 |
2752 #endif | 2682 #endif |
2753 | 2683 |
2754 } } // namespace v8::internal | 2684 } } // namespace v8::internal |
2755 | 2685 |
2756 #endif // V8_TARGET_ARCH_IA32 | 2686 #endif // V8_TARGET_ARCH_IA32 |
OLD | NEW |